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INTEGRATED CIRCUITS
DATA SHEET
SAA7390 High performance Compact Disc-Recordable (CD-R) controller
Preliminary specification File under Integrated Circuits, IC01 1996 Jul 02
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 10 10.1 10.2 11 FEATURES General Interface logic (CD-ROM operation) Hardware third-level error correction Interface logic (CD-R operation) DRAM buffer controller (256 kbytes x 8, 1 Mbyte x 8, 4 Mbytes x 8) Additional product support GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Input clock doubler Block encoder Front-end Track descriptor block Buffer manager MICROCONTROLLER INTERFACE Microprocessor interface status register Microcontroller interface command register Microprocessor interrupts Microcontroller RAM organization FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS S2B UART registers SPI UART registers Track Descriptor Block (TDB) generation Miscellaneous control registers FRONT-END Minute-second frame addressing and header information Front-end status and control BUFFER MANAGER 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16 17 17.1 17.2 17.3 17.4 18 19
SAA7390
Front-end to buffer manager interface Microcontroller to buffer manager interface ECC to buffer manager interface SCSI to buffer manager interface Miscellaneous buffer manager considerations Host interface related registers CDB2 related registers FRAME BUFFER ORGANIZATION SUMMARY OF CONTROL REGISTER MAP LIMITING VALUES OPERATING CHARACTERISTICS I2S-bus timing; data mode EIAJ timing; audio mode R-W timing (see Fig.17) C-flag timing (see Fig.18) S2B interface timing SPI interface timing Microprocessor interface Host interface DRAM interface (the SAA7390 is designed to operate with standard 70 ns DRAMs) PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
1996 Jul 02
2
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
1 1.1 FEATURES General
SAA7390
* Dedicated Serial Peripheral Interface (SPI) * Third level error correction and encoding * 80C32 microcontroller interface * 53CF90 or 53CF92A/B fast SCSI processor interface (may also use ATAPI processor). 2 GENERAL DESCRIPTION
* 8x speed CD-ROM, 4x speed Compact Disc-Recordable (CD-R) controller * 16.9 Mbytes/s burst rate to host controller * High performance CD-ROM and CD-R interface logic * 128 pin QFP package. 1.2 Interface logic (CD-ROM operation)
* Full 8x speed hardware operation * Block decoder * Sector sequencer * CRC checking of Mode 1 and Mode 2, Form 1 sectors * 212 ms watch-dog timer * Sub-code interface with synchronization * C-flag interface for absolute time stamp. 1.3 Hardware third-level error correction
The SAA7390 is a high integration ASIC that incorporates all of the logic necessary to connect a CD-60 based decoder to a SCSI or ATAPI host. It also supports a data path from the host to the CDCEP (compact disc encoder) for CD-R applications. An 80C32 microcontroller and a 53CF94/92A (or an ATAPI interface device) are required to provide the full block encode/decode functions. The following functions are supported: * Input clock doubler * Block encoder (using a modified CDB2) * Block decoder * CRC checking of Mode 1 and Mode 2, Form 1 sectors * Red book audio pass through to SCSI or ATAPI * Sub-code and Q-channel support * Dedicated S2B interface UART * Dedicated SPI interface UART * Up to 4 Mbytes DRAM buffer manager * Third-level error correction and encoding * Automatic storage of audio and data * 80C32 microcontroller interface * 53CF90 or 53CF92A/B fast SCSI or Wapiti ATAPI processor interface. The SAA7390 uses a 33.8688 MHz clock and is capable of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the normal CD-ROM data rate. The minimum host burst rate capability of the SAA7390 is 5 Mbytes/s. Third level error correction hardware is included to improve the correction efficiency of the system. The buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the static microcontroller to emulate a wait condition when necessary. The host interface is capable of burst rates to 16.9 Mbytes/s.
* Third-level correction provides superior performance in unfavourable conditions * Full hardware error correction to reduce microcontroller overhead * Corrections are automatically written to the DRAM frame buffer. 1.4 Interface logic (CD-R operation)
* Block encoder (using a modified CDB2). 1.5 DRAM buffer controller (256 kbytes x 8, 1 Mbyte x 8, 4 Mbytes x 8)
* DRAM buffer manager * Ten level arbitration logic * Utilizes low cost 70 ns DRAMs * Page mode DRAM access for high-speed error correction and host interface data transfers * Data organization by 3 kbytes frames. 1.6 Additional product support
* Input clock doubler * All control registers mapped into 80C32 special function memory space * Red book audio pass through to host interface * Sub-code and Q-channel support 1996 Jul 02 3
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
The SAA7390 comprises four major functional blocks: * The front-end block connects to the external CD-60 based decoder and fully processes the incoming data stream * The buffer manager block provides the address generation and timing control for the external DRAMs * The ECC block performs the error correction functions in hardware on the data stored in the DRAM buffer. * The block encoder function (realized via a modified CDB2) serializes the data from the buffer, appends the sync pattern, header, sub-header, third level ECC parity and EDC bytes as necessary, performs the required scrambling and outputs them to the CDCEP using a special data clock (98 clock cycles per word selection period). 3 QUICK REFERENCE DATA SYMBOL VDD Tamb Tstg 4 PARAMETER digital supply voltage operating ambient temperature storage temperature 4.5 0 -55 MIN. - - TYP. 5.0
SAA7390
MAX. 5.5 70 +150 V
UNIT C C
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SOT387-2
SAA7390GP(1) Note
SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm
1. This device uses a Symbios logic package.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
5 BLOCK DIAGRAM
SAA7390
handbook, full pagewidth
256K x 8 to 4M x 8 DRAM BUFFER
BUFFER MANAGER data subcode LAYERED ERROR CORRECTOR BUFFER MAPPER GENERIC EXTERNAL INTERFACE SCSI or ATAPI interface
DATA CONVERTER AND SUB-CODE UART data subcode C-flag
ENCODE
CD DECODER
MICROCONTROLLER INTERFACE
BASIC ENGINE
WRITE I/F
SAA7390
SPI UART
S2B UART
S2B interface
MGE518
SPI interface 80C32 MICROCONTROLLER
128K x 8 ROM
Fig.1 Block diagram (simplified).
6 PINNING All input and bidirectional signals are TTL level with Schmitt-trigger logic, with the exception of OSCIN. All output signals are TTL levels unless otherwise stated. (PD = internal pull-down; PU = internal pull-up). SYMBOL DA0 DA1 DA2 VSS1 DA3 DA4 DA5 VSS2 DA6 PIN 1 2 3 4 5 6 7 8 9 I/O O O O - O O O - O TYPE DESCRIPTION DRAM address bus; bit DA0 DRAM address bus; bit DA1 DRAM address bus; bit DA2 ground 1 DRAM address bus; bit DA3 DRAM address bus; bit DA4 DRAM address bus; bit DA5 ground 2 DRAM address bus; bit DA6
1996 Jul 02
5
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SYMBOL DA7 VDD1 DA8 DA9 DA10 RAS CAS DWR DOE DD0 VDD2 DD1 DD2 DD3 DD4 VSS3 DD5 DD6 DD7 COM_IN COM_OUT COM_CLK COM_ACK TRAYSW EJECT LQDATA LWCLK VDD3 LED VSS4 SCLK VSS5 SYSRES SYSRES VDD4 GPIO3 GPIO4 VOLUP VOLDN UC_AD0 UC_AD1 1996 Jul 02 PIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O O - O O O O O O O I/O - I/O I/O I/O I/O - I/O I/O I/O I O O I I I O O - O - O - O O - I/O I/O I I I/O I/O PD PD PU PU PU PU PD PD PD PD PD PD PD PD TYPE power supply 1 DRAM address bus; bit DA8 DRAM address bus; bit DA9 DRAM address bus; bit DA10 DRAM row address section; active LOW DRAM column address selection; active LOW DRAM write; active LOW DRAM output enable; active LOW DRAM data bus; bit DD0 power supply 2 DRAM data bus; bit DD1 DRAM data bus; bit DD2 DRAM data bus; bit DD3 DRAM data bus; bit DD4 ground 3 DRAM data bus; bit DD5 DRAM data bus; bit DD6 DRAM data bus; bit DD7 serial data in from basic engine serial data out to basic engine serial data clock serial data acknowledge active LOW when tray is in opens tray; active LOW latched qualified data latched word clock power supply 3 DESCRIPTION DRAM address bus; bit DA7
SAA7390
CMOS; 24 mA panel LED; active LOW; open drain; 24 mA (min.) sink capability ground 4 audio data clock ground 5 system reset; active HIGH system reset; active LOW power supply 4 general purpose input/output 3 general purpose input/output 4 volume up; active LOW volume down; active LOW microprocessor multiplexed address/data bus; bit UC_AD0 microprocessor multiplexed address/data bus; bit UC_AD1 6
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SYMBOL UC_AD2 UC_AD3 VSS6 UC_AD4 UC_AD5 UC_AD6 UC_AD7 VDD5 UC_LA0 UC_LA1 UC_LA2 VSS7 UC_LA3 UC_LA4 UC_LA5 UC_LA6 UC_LA7 VSS8 PCLK VDD6 ALE UC_WR UC_RD INT UC_A8 UC_A9 UC_A10 SYS_SYNC UC_A11 UC_A12 UC_A13 COM_SYNC UC_A14 UC_A15 SD0 VDD6 SD1 SD2 VSS9 SD3 SD4 1996 Jul 02 PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 I/O I/O I/O - I/O I/O I/O I/O - O O O - O O O O O - O - I I I O I I I I I I I I I I I/O - I/O I/O - I/O I/O CMOS TYPE DESCRIPTION
SAA7390
microprocessor multiplexed address/data bus; bit UC_AD2 microprocessor multiplexed address/data bus; bit UC_AD3 ground 6 microprocessor multiplexed address/data bus; bit UC_AD4 microprocessor multiplexed address/data bus; bit UC_AD5 microprocessor multiplexed address/data bus; bit UC_AD6 microprocessor multiplexed address/data bus; bit UC_AD7 power supply 5 latched lower address; bit UC_LA0 latched lower address; bit UC_LA1 latched lower address; bit UC_LA2 ground 7 latched lower address; bit UC_LA3 latched lower address; bit UC_LA4 latched lower address; bit UC_LA5 latched lower address; bit UC_LA6 latched lower address; bit UC_LA7 ground 8 33.8688 MHz microprocessor clock power supply 6 address latch enable write enable read enable interrupt to microcontroller; active LOW; open drain upper address; bit UC_A8 upper address; bit UC_A9 upper address; bit UC_A10 system synchronization from basic engine upper address; bit UC_A11 upper address; bit UC_A12 upper address; bit UC_A13 communication synchronization from basic engine upper address; bit UC_A14 upper address; bit UC_A15 internal data bus; bit SD0 power supply 6 internal data bus; bit SD1 internal data bus; bit SD2 ground 9 internal data bus; bit SD3 internal data bus; bit SD4 7
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SYMBOL SD5 SD6 SD7 VSS10 DREQ DACK HOSTRD HOSTWR HOSTSEL CSAB CCLAB CDAAB RXS2B TXS2B CPR SCSIRST POR TCL_GPIO1 SPR TDA_GPIO2 HFD KILL VSS11 MCOUT MCIN RXSUB CFLAG VSS12 OSCIN VDD7 CLAB DAAB WSAB EFAB VSS13 CLK34 VDD8 PIN 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 I/O I/O I/O I/O - I O O O O I I O I O O I I I/O I I/O I I - O I I I - I - I I I I - O - PD PU PU PU PD PD PU PD TYPE DESCRIPTION internal data bus; bit SD5 internal data bus; bit SD6 internal data bus; bit SD7 ground 10 DMA request DMA acknowledge; active LOW read enable; active LOW write enable; active LOW chip select; active LOW word strobe for write data clock for write data write data stream receive data transmit data ready to accept data; active LOW reset from SCSI bus; active LOW power-on reset; active LOW
SAA7390
general purpose input/output 1 (also used as test-mode clock) ready to send data; active LOW general purpose input/output 2 (also used as test-mode data) laser on and focused status; active LOW mute audio; active LOW ground 11 motor control output from PWM motor control input from decoder sub-code input C1 and C2 status ground 12 input clock from decoder power supply 7 clock input data input word strobe input error flags ground 13 33.8688 MHz output clock power supply 8
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
82 COM_SYNC
100 HOSTSEL
78 SYS_SYNC
99 HOSTWR
98 HOSTRD
84 UC_A15
83 UC_A14
81 UC_A13
80 UC_A12
79 UC_A11
77 UC_A10
67 UC_LA7
66 UC_LA6
102 CCLAB
101 CSAB
73 UC_RD
76 UC_A9
75 UC_A8
96 DREQ 95 VSS10
97 DACK
86 VDD6 85 SD0
71 ALE 70 VDD6
69 PCLK 68 VSS8
89 VSS9
handbook, full pagewidth
65 UC_LA5 64 UC_LA4 63 UC_LA3 62 VSS7 61 UC_LA2 60 UC_LA1 59 UC_LA0 58 VDD5 57 UC_AD7 56 UC_AD6 55 UC_AD5 54 UC_AD4 53 VSS6 52 UC_AD3 51 UC_AD2 50 UC_AD1 49 UC_AD0 48 VOLDN 47 VOLUP 46 GPIO4 45 GPIO3 44 VDD4 43 SYSRES 42 SYSRES 41 VSS5 40 SCLK 39 VSS4 LED 38
MGE517
CDAAB 103 RXS2B 104 TXS2B 105 CPR 106 SCSIRST 107 POR 108 TCL_GPIO1 109 SPR 110 TDA_GPIO2 111 HFD 112 KILL 113 VSS11 114 MCOUT 115 MCIN 116 RXSUB 117 CFLAG 118 VSS12 119 OSCIN 120 VDD7 121 CLAB 122 DAAB 123 WSAB 124 EFAB 125 VSS13 126 CLK34 127 VDD8 128 DA7 10 VDD1 11 DA8 12 DA9 13 DA10 14 RAS 15 CAS 16 DWR 17 DOE 18 DD0 19 VDD2 20 DD1 21 DD2 22 DD3 23 DD4 24 VSS3 25 DD5 26 DD6 27 DD7 28 COM_IN 29 COM_OUT 30 COM_CLK 31 COM_ACK 32 TRAYSW 33 EJECT 34 LQDATA 35 LWCLK 36 VDD3 37 1 2 3 4 5 6 7 8 9
SAA7390
VSS1
DA0
DA1
DA2
DA3
DA4
DA5
VSS2
DA6
Fig.2 Pin configuration.
1996 Jul 02
9
72 UC_WR
94 SD7
93 SD6
92 SD5
91 SD4
90 SD3
88 SD2
87 SD1
74 INT
dbook, full pagewidth
1996 Jul 02
DISC MOTOR CONTROLLER CDR650 COMPACT DISC DECODER RAM TDA8425 AUDIO PROCESSOR LO9465 left output S83C752 right output
Philips Semiconductors
CD LOADER L2465
SIGNAL PROCESSOR COMPACT DISC ENCODER DAC TDA1545A TDA1371 SAA7390 WAPITI 53CF90 53CF92A 53CF92B DIGITAL SERVO DRIVERS SERVO MICRO OQ8844 OQ8845 DIGITAL SERVO CONTROLLER CD-ROM MICRO 80C32
MGE519
High performance Compact Disc-Recordable (CD-R) controller
TDA1372
CD-ROM ENCODER AND DECODER
10
ATAPI interface SCSI-2 interface ATAPI/SCSI INTERFACE
3-BEAM MECHANISM
CDM24
Preliminary specification
SAA7390
Fig.3 Double-speed write quad-speed play CD-R system D65420 with ATAPI or SCSI-2 interface.
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
7 7.1 FUNCTIONAL DESCRIPTION Input clock doubler
SAA7390
It also detects and tests the synchronization field and will start the data clock when commanded. The de-scrambled header is assembled into four registers with header ready and header error status (see HDRRDY and HDRERR in RDDSTAT). The data clock does not have to be enabled to receive valid headers. Also included in this section is the logic required to decide when to automatically start collecting data and sub-code information based on the contents of the Q-channel registers. 7.3.2 SECTOR SEQUENCER
To facilitate compatibility of the SAA7390 with all of the available CD decoders, a clock doubler has been included. This clock doubler may take a 16.9344 MHz clock and double this when requested to do so by the microcontroller. Logic has been included to remove the possibility of a `runt' clock pulse when the doubler is engaged. Once engaged, the only way to disengage it is via a reset condition. 7.2 Block encoder
To support the write function, a modified version of the CDB2 function has been included. The block encoder accepts parallel data from the buffer manager, serializes it, calculates the CRC and third-level ECC parity bytes and appends them when and where necessary. The RAM required during the parity calculation is included on the SAA7390. The following modifications to the CDB2 have been made: * Word select in bypass mode has been inverted to match the data mode * The `end-of-frame' signal is now generated during the bypass and CD-ROM mode and will interrupt the microcontroller at the end of each frame * The `end-of-frame' signal is also used to correctly synchronize between bypass mode and regular data mode at the end of a frame. The modes programmed into the CDB2 command, header, sub-header and block size registers will automatically switch in or out at the end of frame * DRQ in CCMD is also synchronized to frame boundaries using the `end-of-frame' signal. This change is valid for both bypass and regular data modes. 7.3 Front-end
The sector sequencer de-serializes the data and error flags from the block decoder and determines when to: * Write data to the buffer * Write flags to the buffer * Test the header to determine the Mode * Test the sub-header to determine the Form * Test the CRC * End the sector and write the status byte to the buffer. Included in the sector sequencer is the CRC generator which checks each Yellow book or Green book sector as it is shifted into the SAA7390 in accordance with the following polynomial: X32 + X31 + X16 + X15 + X4 + X3 + X + 1 The status of each sector is saved and written to the buffer at the end of the sector. 7.3.3 SUB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR
The front-end section of the SAA7390 is identical to the front-end of the mini-SEQUOIA (also found on the SAA7385), with the exception of the Serial Peripheral Interface (SPI). The front-end is comprised of many sub-sections. 7.3.1 BLOCK DECODER
A UART which samples asynchronous bits on a 24 clocks per bit basis is included. This is required because the CD-60 based decoders output the sub-code data at nominally 24 clocks per bit, but not synchronized to the data. Also included is a sub-code synchronization detector which senses the beginning of each new sector of sub-code information. The serial sub-code information is assembled into bytes in the following order: Data bits 7 to 0 = 0, Q, R, S, T, U, V and W. As each byte is assembled, it is sent to the buffer manager to be written to the DRAM buffer. At the same time, the Q-channel bits are assembled into bytes and sent to the buffer. All Q-channel bytes except CRC are sorted in registers for use by the microcontroller. The Q-channel CRC (last two bytes) is checked just before the end of the sub-code sector. If the CRC check fails, BADQ in RDDSTAT is available to the microcontroller and is written into the buffer at the end of the sector. 11
The block decoder first reverses the bits of each received byte and then runs them through a linear feedback shift register to be de-scrambled. The polynomial used to de-scramble the serial data is as follows: X15 + X + 1
1996 Jul 02
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
When the ten Q-channel registers have been updated, QFRMRDY in RDDSTAT is set. The ten Q-channel registers are valid while QFRMRDY is set. In the audio mode, HDRRDY in RDDSTAT generates this interrupt, but the QFRMRDY bit will still be available as status to the microcontroller. 7.3.4 C-FLAG RECEIVER 7.3.6 SPI UART
SAA7390
This UART is provided for communication with a second slave microcontroller used in Philips CD-R engines. 7.3.7 WATCH-DOG TIMER
The C-flag bits, or corrector flags, are also 24 data clocks long and reception of these bits is achieved using the same method as for the sub-code; in this event, the C-flag data is synchronized to the data. The difference is that only one bit is used; F1, the absolute time synchronization information. When in audio mode and ENABRED in FECTL is set, receipt of F1 set will start the internal data clock after the next rising edge of word strobe (WSAB) which is the left channel sample when the CD-60 decoder is programmed for EIAJ audio format. When in audio mode, the Q-channel information provides the MSF address and the F1 flag provides the start of frame information; together these provide an absolute byte address on the disc. 7.3.5 S2B UART
A pair of counters are included which output a 967 s reset pulse to the entire chip and the SYSRES and SYSRES pins if the timer is not reset during the 212 ms time-out period. The watch-dog timer is reset by setting RWMD in FECTL HIGH then LOW. If RWMD is left HIGH, the watch-dog function is disabled. 7.3.8 GLUE LOGIC (GLIC)
The final block of logic in the front-end consists of: a programmable, linear pulse-width modulator for spindle-motor control; an address de-multiplexer for the address/data bus of the microcontroller; plus audio multiplexing and muting circuitry for full control of Red book audio data to an external Digital-to-Analog Converter (DAC). 7.4 Track descriptor block
This UART is provided for communication with a second slave microcontroller. It is hard-wired for one start-bit, eight data bits, a parity bit and one stop bit. Parity testing can be programmed to be either odd parity or even parity. Parity error and over-run status are provided via PE and OVRRUN in S2BSTAT. Selectable baud rates of 31.25, 62.5 and 187.5 kbaud are available via S2BSEL1 and S2BSEL0 in BRGSEL. Once the start-bit is found, the data sampling time does not adapt dynamically, therefore parity errors may occur depending on the baud rate selected.
Logic has been included to simplify the creation of the track descriptor block. This is achieved by allowing one frame to be repeated a selectable number of times. Once this repeated pattern is complete, the normal data is then sent to the front-end.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
7.5 Buffer manager
SAA7390
A burst access by ECC or host interface will only be interrupted by a higher priority access request. In addition to the priority logic, logic is required for the front-end sources of data. The priority is; CDB2 requests (highest) frame data, flag data, sub-code data, Q-channel data and finally status byte. All front-end sources are granted priority over the host interface logic, ECC, refresh and data will be written into the frame store during the next cycle. However, the microcontroller has priority over the lower three front-end sources and will be granted an access after front-end frame data or flag data is written to memory. The required timing (see Figs 4 to 11) operate with the industry standard 70 ns DRAMs. The interface is designed to operate with 256 kbytes, 1 Mbyte, and 4 Mbytes of DRAM. A single byte access cycles requires five clock cycles of 29.5 ns each, totalling 147.5 ns.
The buffer manager provides the arbitration for the different processes that wish to access the DRAM buffer. These processes include the front-end, microcontroller requests, CDB2 accesses, ECC accesses, host interface requests and DRAM refreshing. To manage a DRAM interface with up to four devices requesting access to the DRAM, the following priority scheme is used. The DRAM control logic will start an access on the next rising edge of the clock after a request is received. If two or more requests are pending then the priority is: 1. Front-end (highest priority) 2. A refresh cycle (required every 15.6 s) granted priority for one access 3. Microcontroller requests 4. Host interface requests 5. ECC requests (lowest priority).
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL latch data
DOE
MGE392
Fig.4 Byte mode single access read cycle.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL DATA
WRITE
MGE393
Fig.5 Byte mode single access write cycle.
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL1 latch COL2 latch COL3 latch COL4
DOE
MGE394
Fig.6 ECC burst access read cycle.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL1 DATA1 COL2 DATA2 COL3 DATA3 COL4 DATA4
WRITE
MGE395
Fig.7 ECC burst access write cycle.
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL1 latch data COL2 latch data COL3 COL4 latch data
DOE
MGE396
Fig.8 Host interface fast burst access read cycle (2 clocks).
1996 Jul 02
15
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
CLOCK RAS
CAS ADDRESS DATA ROW COL1 DATA1 COL2 DATA2 COL3 DATA3 COL4 DATA4
WRITE
MGE397
Fig.9 Host interface fast burst access write cycle (2 clocks).
handbook, full pagewidth
CLOCK QA QB QC RAS
CAS ADDRESS DATA ROW COL1 latch data COL2 latch data COL3 COL4 latch data
DOE
MGE520
Fig.10 Host interface standard burst access read cycle (3 clocks).
1996 Jul 02
16
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
CLOCK QA QB QC RAS
CAS ADDRESS DATA ROW COL1 DATA1 COL2 DATA2 COL3 DATA3 COL4 DATA4
WRITE
MGE521
Fig.11 Host interface standard burst access write cycle (3 clocks).
8 8.1
MICROCONTROLLER INTERFACE Microprocessor interface status register NUM_COR register: 0xF08E; note 1 DATA BYTE MNEMONIC NUM_COR R/W 7 R 6 5 4 3 2 1 0 NUM_COR7 to NUM_COR0
Table 1
Note 1. Register 0xF08E indicates the number of corrections performed during the most recently executed CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command. Note that NUM_COR is only valid after completion of the CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command, and becomes invalid upon execution of any other command. Table 2 ECC_STATUS register: 0xF086; note 1 DATA BYTE MNEMONIC ECCSTAT Note 1. Register 0xF086 provides status information on the current or last ECC command. R/W 7 R - 6 - 5 - 4 FLG_EQ0 3 CRC_EQ0 2 PS_EQ0 1 QS_EQ0 0 ECC_ACT
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 3 ECCSTAT definitions DESCRIPTION
SAA7390
MNEMONIC ECC_ACT QS_EQ0 PS_EQ0 CRC_EQ0 FLG_EQ0 8.2 asserted when all Q syndromes are zero asserted when all P syndromes are zero
asserted while a command other than ASSERT_ABORT or RELEASE_ABORT remains active
asserted when the CRC remainder calculated by the CRC_CALCULATE command is all zeros asserted when all flag bytes in ECC RAM are zero
Microcontroller interface command register ECCCTL register: 0xF085; note 1 DATA BYTE MNEMONIC ECCCTL R/W 7 R/W - 6 - 5 - 4 - 3 2 1 0 ECC_COMMAND3 to ECC_COMMAND0
Table 4
Note 1. The ECC_COMMAND definitions are explained in Table 5. Table 5 Definitions of ECC_COMMAND3 to ECC_COMMAND0 DESCRIPTION ASSERT_ABORT RELEASE_ABORT CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES CORRECT_Q_SYNDROMES TEST_ECC_ROM TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE
EEC_COMMAND 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 Table 6
Command descriptions COMMAND DESCRIPTION Terminates any currently active operation and re-initializes the ECC logic. Remains in reset state until occurrence of the RELEASE_ABORT command. At power-on reset, the ECC is in the ASSERT_ABORT state. All microprocessor status bits are reset when the ECC is in the ASSERT_ABORT state. Terminates the ASSERT_ABORT command and enables activation of other commands.
ASSERT_ABORT
RELEASE_ABORT
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
COMMAND CRC_RECALCULATE DESCRIPTION
SAA7390
Calculate CRC remainder buffer data, storing result in ECC RAM and updating microprocessor status bit CRC_EQ0. Mode 2, Form 1 uses address 16 : 2075, or 0 : 2067; note 1 Prepares buffer for correction, calculates P and Q syndromes, and copies error flags and CRC remainder from buffer to ECC RAM. The microprocessor status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. 1. Copy header from buffer to ECC RAM (Mode 2, Form 1 only) 2. Write to the buffer. Not Mode 2, Form 1: Address 0 0x00; Address 1 : 10 0xFF; Address 11 0x00; Address 2068 : 2075 0x00 Mode 2, Form 1: Address 0 0x00; Address 1 : 10 0xFF; Address 11 : 15 0x00 3. Read header and frame data from buffer to calculate P and Q syndromes psyn[0 : 85].s1, psyn[0 : 85].s0, qsyn[0 : 51].s1 and qsyn[0 : 51].s0, storing results in ECC RAM 4. Copy error flags from buffer to ECC RAM 5. Copy CRC remainder from buffer to ECC RAM 6. Update microprocessor status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0.
CALCULATE_SYNDROME S
COPY_RESULTS
Copies current ECC RAM contents to the buffer memory: 1. Copy header flags from ECC RAM to buffer (Mode 2, Form 1 only) 2. Copy error Flags from ECC RAM to buffer 3. Copy CRC remainder from ECC RAM to buffer 4. Copy P syndromes from ECC RAM to buffer 5. Copy Q syndromes from ECC RAM to buffer.
CORRECT_P_SYNDROME Scan all P syndromes and perform P-syndrome calculation. The microprocessor status S bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. CORRECT_Q_SYNDROME Scan all Q syndromes and perform Q-syndrome calculation. The microprocessor S status bits PS_EQ0, QS_EQ0 and FLAGS_EQ0 are updated at the end of this operation. TEST_ECC_ROM TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE Note 1. 16 : 2075 and 0 : 2067 are address frame offsets. The frame buffer organization is shown in Table 76. Read each exponent and log in the alpha ROM to the NUM_COR register. This command may only be terminated by the ASSERT_ABORT command. Read ECC RAM addresses 0 : 591 and copy to buffer addresses 0 : 591. Read buffer addresses 0 : 591 and copy to ECC RAM addresses 0 : 591.
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
8.3 Microprocessor interrupts
SAA7390
An interrupts pulse is generated upon completion of any of the following commands: * CALCULATE_SYNDROMES (not Mode 2, Form 1) * CALCULATE_SYNDROMES (Mode 2, Form 1) * CRC_RECALCULATE (not Mode 2, Form 1) * CRC_RECALCULATE (Mode 2, Form 1) * COPY_RESULTS (not Mode 2, Form 1) * COPY_RESULTS (Mode 2, Form 1) * CORRECT_P_SYNDROMES * CORRECT_Q_SYNDROMES * TEST_ECC_ROM * TEST_ECC_RAM_READ * TEST_ECC_RAM_WRITE. If a command is aborted by the ASSERT_ABORT command, a spurious interrupt may be generated within five clock cycles of the ASSERT_ABORT command. Table 7 Command execution times; note 1 COMMAND CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES (maximum addition per correction) CORRECT_Q_SYNDROMES (maximum addition per correction) TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE Note 1. All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections. P and Q corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh timing, other buffer traffic, and configuration of nibble-wide memory. 8.3.1 INTERRUPT REGISTER DEFINITIONS CYCLES 5604 5600 4136 4120 1148 1156 1466 157 888 167 1184 1184 TIME (s) at 33 MHz 186.8 186.7 137.9 137.3 38.3 38.5 48.9 5.2 29.6 5.6 39.5 39.5 MEMORY ACCESSES 2658 2654 2068 2060 574 578 0 2 0 2 592 592
Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt, the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
bit location in INTRFLG will clear the corresponding interrupt. If a masked interrupt occurs, the microcontroller can still detect the occurrence because the event is still posted in INTRFLG. Table 8 Interrupt mask register: 0xF0FB DATA BYTE MNEMONIC INTRMSK R/W 7 R/W MASK7 6 MASK6 5 MASK5 4 MASK4 3 MASK3 2 MASK2 1 MASK1 0 MASK0
Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an interrupt, the bit in this register must be set HIGH. Table 9 Interrupt flag register: F0FC; note 1 DATA BYTE MNEMONIC INTRFLG Note 1. If any bit is set in this register an interrupt is sent to the microcontroller. Table 10 shows when the interrupts are asserted; assuming the corresponding mask bit is set. Table 10 INTRFLG field descriptions FIELD FRM_STR STR_LST FE_2352 FE_HDR ECC_COR RFERXINT FETXINT CDB2INT 8.4 set at the start of the last frame set if the front-end data exceeds 2352 bytes front-end interrupt for header (or Q channel) ready ECC interrupt for correction complete front-end interrupt for receive ready front-end interrupt for transmit ready CDB2 interrupts: see CSTAT (Table 78) for bit descriptions space between 0x000 and 0x7FFF. If this 32 kbytes page is used, the PAGEREG must be programmed with the required page address. PAGEREG is used to select the required page when the microcontroller makes a linear access to the buffer memory using the address space 0x7000 to 0x7FFF. The actual address is the fifteen LSBs from the microcontroller plus 32768 times the value in PAGEREG. DESCRIPTION set one when one complete frame is stored R/W 7 R/W 6 5 FERXINT 4 3 2 FE2352 1 0 CDB2INT FETXINT ECC_COR FE_HDR STR_LST FRM_STR
Microcontroller RAM organization
MICFRM# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to 0x8FFF. To obtain the actual byte location within the buffer RAM, the lower 12 bits of the microcontroller address form the relative offset and hence the absolute address is found. Note that the microcontroller has the option of addressing memory in a linear fashion using the 32 kbytes address
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 11 Microcontroller frame number address registers: 0xF0F6 and 0xF0F7; note 1 DATA BYTE MNEMONIC MICFRM# MICFRM# Note R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1
SAA7390
0 FRAME0 FRAME8
FRAME1
FRAME10 FRAME9
1. Registers 0xF0F6 and 0xF0F7 provide the frame number address for the microcontroller access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is complete. Table 12 Microcontroller address page register: 0xF0FF; note 1 DATA BYTE MNEMONIC PAGEREG Note 1. Register 0xF0FF is used by the buffer manager for the upper address lines when the microcontroller addresses non-frame memory. These registers overlap frame memory, so register 0xF0FF must be programmed with an address in the top part of the memory if no overlap is required. The microcontroller page address line is selected from this register. The outputs are used directly to control DRAM access cycles, and will affect any current DRAM cycle in progress. It is possible to access three contiguous frames from the microcontroller by reading the three data sector windows, 0x8000 to 0x8FFF, 0x9000 to 0x9FFF and 0xA000 to 0xAFFF. This function is required for the decoding of the sub-code information. If the `next' frame wraps past the last frame pointer (LASTFRM) then the pointers are modified to wrap back to the start pointer onwards (FEFRM#); this section is transparent to the microcontroller. R/W 7 R/W - 6 MA_21 5 MA_20 4 MA_19 3 MA_18 2 MA_17 1 MA_16 0 MA_15
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, halfpage 0000
80C32 SCRATCH PAD RAM
7FFF 8000
DATA SECTOR WINDOW (FRAME 0) DATA SECTOR WINDOW (FRAME 1) DATA SECTOR WINDOW (FRAME 2)
9000
A000 AFFF
F000 FFFF
SAA7390 CONTROL REGISTERS
MGE522
Fig.12 Address map for the microcontroller.
Table 13 SAA7390 address map details for the 80C32 ADDRESS 0000 to 7FFF FUNCTION This 32 kbytes window is used to address and portion the DRAM buffer. It is intended for non-frame mapped memory to be addressed through this window. The upper page address bits (to address the full range of the DRAM buffer) are set by the linear address page register (PAGEREG). All accesses to frame memory use this window to read or write to the buffer memory. The actual address to the DRAM buffer is Micro Frame Number (MICFRM#) times 3 k plus the 12 LSBs from the 80C32. This frame window is identical to the frame 0 window with the exception that one is added to the value from the Micro Frame Number (MICFRM#). This frame window is identical to the frame 0 window with the exception that two is added to the value from the Micro Frame Number (MICFRM#). Not used; output 3-state. SAA7390 control registers.
8000 to 8FFF
9000 to 9FFF A000-AFFF B000-EFFF F000-FFFF
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
9 FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS
SAA7390
This Chapter describes the various SAA7390 control signals; front panel and basic engine signals, jumper settings and use of the general purpose signals. Table 14 Start clock doubler: 0xF091 DATA BYTE MNEMONIC CLKSEL R/W 7 W - 6 - 5 - 4 - 3 - 2 - 1 - 0 -
A write of any value to this address will engage the clock doubler. The state of the doubler may be obtained by reading C_34_16 in BRGSEL (see Table 26). If this bit is set then the clock doubler is engaged. On power-on, the clock doubler is disabled. Once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, an SCSI reset or a reset from the watch-dog timer. The clock doubler must not be engaged when a 34.8688 MHz clock is connected to OSCIN (pin 120). Table 15 General logic control register: 0xF0B9; note 1 DATA BYTE MNEMONIC WTGCTL Note 1. Register 0xF0B9 controls the audio mixing, the LED and the PWM control. Table 16 WTGCTL field descriptions FIELD CHANNELS LOGIC 00 01 10 11 RA_MUTE LA_MUTE LED PWMSEL - - - 0 1 mute right data sent to both channels left data sent to both channels stereo right channel digital mute left channel digital mute active LOW control for the light emitting diode CD decoder output (default); e.g. CD-60 MOTO1 output PWM output DESCRIPTION R/W 7 W - 6 - 5 PWMSEL 4 LED 3 2 1 0 LA_MUTE RA_MUTE CHANNEL1 CHANNEL0
Table 17 Drive switches register: 0xF0BA; note 1 DATA BYTE MNEMONIC RDSW Note 1. Register 0xF0BA is used for sensing the drive switches (note that the meaning of the switches is application specific). R/W 7 R - 6 - 5 - 4 HFD 3 VOLUP 2 VOLDN 1 EJECT 0 TRAYSW
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 18 RDSW field descriptions FIELD TRAYSW EJECT VOLDN VOLUP HFD LOGIC 0 1 - - - - tray position in tray position out user is requesting the drive tray to open (active LOW) user is requesting a decrease in volume (active LOW) user is requesting an increase in volume (active LOW) high frequency detection; laser is on and focused (active LOW) DESCRIPTION
SAA7390
Table 19 Jumper status register: 0xF0C9; note 1 DATA BYTE MNEMONIC RDJMPRS Note 1. The bit fields for the jumpers are explained in Table 21 (note that the meaning of the jumpers is application specific). Table 20 RDJMPRS field descriptions FIELD SCSIID PAREN ALO/PRE DESCRIPTION SCSI identity. Installing pull-up shunts on the ID selection jumpers (DD2 to DD) sets the respective SCSI ID bits HIGH on de-assertion of reset. SCSI bus parity enable. Installing a pull-up shunt on DD3 sets this bit HIGH on de-assertion of reset. The firmware should interpret this as SCSI bus parity enable. Allow/Prevent. Installing a pull-up shunt on DD4 sets this bit HIGH on de-assertion of reset. Drive firmware interprets this as allowing access to media. R/W 7 R 6 RESERVED (2 to 0) 5 4 ALO/PRE 3 PAREN 2 SCSIID2 1 SCSIID1 0 SCSIID0
Table 21 General purpose bits: 0xF0C2; note 1 DATA BYTE MNEMONIC GPIOCTL Note 1. Register 0xF0C2 controls the direction and output state of the general purpose I/O bits on the SAA7390. Reading the GPIO direction bits reflects the last value that was written to the register. The four GPIO data bits shows the current value of the input signals in the input mode. In the output mode, the last value written to the output latches is that which is read back. R/W 7 R/W GPDAT4 6 GPDIR4 5 GPDAT3 4 GPDIR3 3 GPDAT2 2 GPDIR2 1 GPDAT1 0 GPDIR1
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 22 GPIOCTL field descriptions FIELD GPDIR1 GPDAT1 GPDIR2 GPDAT2 GPDIR3 GPDAT3 GPDIR4 GPDAT4 9.1 DESCRIPTION
SAA7390
General purpose bit direction control. Default LOW puts GPIO1 into the input mode, setting this HIGH puts GPIO1 in output mode. GPIO1 data bit. General purpose bit direction control. Default LOW puts GPIO2 into the input mode, setting this HIGH puts GPIO2 in output mode. GPIO2 data bit. General purpose bit direction control. Default LOW puts GPIO3 into the input mode, setting this HIGH puts GPIO3 in output mode. GPIO3 data bit. General purpose bit direction control. Default LOW puts GPIO4 into the input mode, setting this HIGH puts GPIO4 in output mode. GPIO4 data bit.
S2B UART registers
This section describes the registers used for the S2B UART control. Table 23 S2B UART transmit, receive and status buffer: 0xF0A1, F0A2 and F0A3; note 1 DATA BYTE MNEMONIC WTS2B RDS2B S2BSTAT Note 1. WTS2B is for the transmit data byte from the S2B UART and RDS2B is for the receive data byte from the S2B UART. Table 24 S2BSTAT field descriptions FIELD RXDRDY OVRRUN PE TXDRDY DESCRIPTION logic 1 indicates that the receive data is valid logic 1 indicates that the data in the receive buffer was not read before it was over written by the next byte logic 1 indicates that a parity error was detected in the receive data byte; this is usually caused by the wrong baud rate logic 1 indicates that the transmit data buffer is empty and ready for another byte R/W 7 W R R DATA7 DATA7 - 6 DATA6 DATA6 - 5 DATA5 DATA5 - 4 DATA4 DATA4 - 3 DATA3 DATA3 TXDRDY 2 DATA2 DATA2 PE 1 DATA1 DATA1 OVRRUN 0 DATA0 DATA0 RXDRDY
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 25 Baud rate generator control: 0xF0C0; note 1 DATA BYTE MNEMONIC BRGSEL Note R/W 7 R/W C_34_16 6 LOCK 5 4 3 INVQ 2 - 1
SAA7390
0
EVENPAR INVSUBC
S2BSEL1 S2BSEL0
1. Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel information. Table 26 BRGSEL field descriptions FIELD S2BSEL1 and S2BSEL0 LOGIC 00 01 10 11 INVQ INVSUBC EVENPAR LOCK C_34_16 9.2 SPI UART registers - - - - - 31.25 kbaud transfer rate 62.5 kbaud transfer rate 187.5 kbaud transfer rate not specified inverts all Q-channel information if set inverts all sub-code information if set selects even parity for S2B UART is set read only information; indicates clock synthesizer is stable (after reset) and it is ready to set C_34_16 once LOCK is HIGH, asserting this bit engages the clock doubler DESCRIPTION
This section describes the registers used for SPI control. Table 27 Serial communication control: 0xF0F1; note 1 DATA BYTE MNEMONIC R/W 7 SC_CTL Note 1. Register 0xF0F1 selects and reports the signals and edges of interrupts required to control the basic engine. The least significant four bits perform the selection and are read/write. If both the rising and falling edges are set then both signal edges cause interrupts. If both rising and falling edges are cleared then neither edge will cause an interrupt. The most significant four bits report which edge of which signal caused the interrupt and are read-only; the interrupt generated by these bits is cleared by reading register 0xF0F1. 6 5 4 3 2 1 0 R/W SSU_REP SSD_REP CSU_REP CSD_REP SSU_SEL SSD_SEL CSU_SEL CSD_SEL
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 28 UARTCTL field descriptions FIELD CSD_SEL CSU_SEL SSD_SEL SSU_SEL CSD_REP CSU_REP SSD_REP SSU_REP elects COM_SYNC falling edge when set selects COM_SYNC rising edge when set selects SYS_SYNC falling edge when set selects SYS_SYNC rising edge when set reports COM_SYNC falling edge when set reports COM_SYNC rising edge when set reports SYS_SYNC falling edge when set reports SYS_SYNC rising edge when set DESCRIPTION
SAA7390
Table 29 SAA7390 to basic engine communication port: 0xF0C4; note 1 DATA BYTE MNEMONIC R/W 7 SERCOM Note 1. Register 0xF0C4 provides a serial communication path to the basic engine processor. Writing a byte to this register automatically clocks the bits to the other processor. As the bits shift out, a byte from the basic engine processor is shifted in. The bit rate is 2 Mbits/s. Handshake with the basic engine is accomplished with COM_ACK. 9.3 Track Descriptor Block (TDB) generation R/W DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0
A special mode has been included to support automatic TDB generation. Basically, the host writes one frame of the TDB into the buffer and programs its address into TDB. Then the number of frames to repeat this pattern is programmed in TDB_CNT. Once this has been carried out, TDB_EN in FEBMCTL is set. When the frame counter equals the contents of TDB, the TDB frame will be repeated as many times as programmed by TDB_CNT. If more than 256 frames are required for the TDB, TDB_CNT can be read back and re-programmed with a new value. This action must be carried out as soon as possible after an end-of-frame to prevent the count value from being corrupted. Table 30 Track descriptor block count: 0xF08F; note 1 DATA BYTE MNEMONIC R/W 7 TDB_CNT Note 1. The loadable down counter holds the TDB frame count. TDB_CNT can be read while a TDB is being sent to the CDB2 and may be re-written with a new value to extend the length of the TDB beyond 256 frames; which should be carried out as soon as possible after an end-of-frame. R/W 6 5 4 3 2 1 0 TDB count 7 to TDB count 0
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 31 Track descriptor block address: 0xF096 and 0xF097; note 1 DATA BYTE MNEMONIC R/W 7 TDB TDB Note R/W R/W - - - 6 5 4 - 3 - 2 1
SAA7390
0
TDB address 7 to TDB address 0 TDB address 10 to 8
1. Registers 0xF096 and 0xF097 contain the frame address of the TDB. When the buffer manager frame count equals the contents of this register and the TDB_EN bit is set in BMFECTL, the frame counter will not be allowed to increment until TDB_CNT equals zero. 9.4 Miscellaneous control registers
Table 32 Host interface direction and audio mode control: 0xF0C1; note 1 DATA BYTE MNEMONIC WTDIR Note 1. Register 0xF0C1 controls the data path to the host interface and some audio functions. Table 33 WTDIR field descriptions FIELD AUTOSTR DESCRIPTION Automatic store; default is off. When set HIGH, the front-end will automatically begin storing data or audio when the contents of the header/Q-channel registers equals the contents of the STRTMIN, STRTSEC and STRTFRM registers. If a header/Q-channel error occurs to invalidate the address, auto-store is inhibited. Storing of data will continue until the contents of the STOPCNT equals zero, at which time it will automatically stop. Host direction; default LOW. This selects the microcontroller data path to the SCSI interface. Setting this HIGH selects the buffer managers DMA path. When using a 53CF92A, this should be set and left HIGH since the microcontroller has a separate command path into the 53CF92A whereas the 53CF90B requires the buffer manager and microcontroller to share the same path. Byte swap bit. Defaults to swapping the most significant byte and least significant byte in the audio mode such that the least significant byte of all audio samples is stored at even addresses in the DRAM. Setting this HIGH causes the audio data to be stored in the same way as in the data mode. 4x over-sampling bit selection; default LOW select transmit, or no over-sampling, mode for the sub-code and C-flag UARTs. Setting this bit HIGH will cause the sub-code and C-flag data to be sampled at one quarter the data rate allowing Q-channel information to be correctly stored in the registers while the CD-60 is outputting audio data at 4x over-sampling. CBD2 byte swap bit; default LOW allows data from the DRAM buffer to be sent to the CDB2 normally (data mode). When set HIGH, the high byte and low byte are swapped since data from the host will be swapped. As a result, Red book in the bypass mode will be correctly aligned. R/W 7 R/W - 6 - 5 - 4 CBSB 3 OVER4X 2 BSB 1 0 HOSTDIR AUTOSTR
HOSTDIR
BSB
OVER4X
CBSB
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 34 SCSI mode control register: 0xF0FD; note 1 DATA BYTE MNEMONIC HOSTMOD Note R/W 7 R/W - 6 SELCF92 5 FAST 4 3 2 OFF_STR 1
SAA7390
0 BYT/PAG
OFF_ADR OFF_END
RD_BUF
1. Register 0xF0FD controls the operation of the interface to the host interface controller. The outputs of these registers are used to directly control DRAM access cycles, and will affect any current DRAM cycle in progress. Table 35 HOSTMOD field descriptions FIELD BYT/PAG RD_BUF OFF_STR OFF_END OFF_ADR FAST SELCF92 LOGIC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 10 FRONT-END This chapter explains the information of the front-end circuitry. 10.1 Minute-second frame addressing and header information DESCRIPTION host interface DRAM byte mode access host interface DRAM page mode access host interface read/write control; read from buffer memory host interface read/write control; write to buffer memory host interface offset start A/B control; select A registers host interface offset start A/B control; select B registers host interface offset end A/B control; select A registers host interface offset end A/B control; select B registers host interface transfers use only A registers host interface transfers use A and B registers 3 cycles host interface burst accesses from buffer 2 cycles host interface burst accesses from buffer DRAM timing optimized for 53CF90 DRAM timing optimized for 53CF92
Table 36 Header mode and MSF from block decoder: 0xF092, F093, F09A and F09B; note 1 DATA BYTE MNEMONIC HDRMODE HDRMINS HDRSEC HDRFRM Note 1. These registers contain the mode, minute, second and frame information from the header when in data mode. This data is valid whenever the HDDRDY bit in the RDDSTAT register is set. In audio mode, the MSF address is taken from the Q-channel information. R/W 7 R R R R 6 5 4 3 2 1 0 MODE7 to MODE0 MINUTES7 to MINUTES0 SECONDS7 to SECONDS0 FRAME7 to FRAME0
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
Table 37 Q-channel information: 0xF084, F094, F095, F0A9, F0AA, F0AB, F0B1, F0B2, F0CF and F0FA,; note 1 DATA BYTE MNEMONIC QZERO QTNO QINDX QMODE QAMIN QASEC QAFRM QMIN QSEC QFRM Note 1. These registers contain the information taken from the raw sub-channel information from the CD decoder. Due to the fact that this data has not had any error correction applied to it, it is necessary to perform a CRC check for validity. Twelve bytes of Q-channel information are assembled from each sector of data; the last two bytes contain the CRC parity. Therefore the validity of the contents of these registers can only be determined after the last bit has been loaded and checked. Table 38 Times from QCHRDY to BADQ (RDDSTAT) SPEED n=1 n=2 n=4 n=6 n=8 TIME (s) 2177 1089 545 363 273 R/W 7 R R R R R R R R R R 6 5 4 3 2 1 0 ZERO7 to ZERO0 TRACK7 to TRACK0 INDEX7 to INDEX0 MODE7 to MODE0 ABSMIN7 to ABSMIN0 ABSSEC7 to ABSSEC0 ABSFRM7 to ABSFRM0 RELMIN7 to RELMIN0 RELSEC7 to RELSEC0 RELFRM7 to RELFRM0
For example, at the n = 4 data rate, the BADQ flag (in RDDSTAT) should be checked 545 s after the QFRMRDY interrupt (from RDDSTAT) is asserted. If BADQ is LOW then the contents of the Q-channel registers are valid; otherwise the CRC check failed and the Q-channel information may be incorrect. If the data clock is running (ECMD LOW or ENABRED HIGH) then BADQ will be valid until the end of the sector; otherwise BADQ is valid until the end of the next Q frame.
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
10.2 Front-end status and control
SAA7390
Table 39 Front-end control: 0xF0BB; note 1 DATA BYTE MNEMONIC FECTL Note 1. Register 0xF0BB controls the front-end of the SAA7390. The naming convention used here is similar to that used in the block decoders. Table 40 FECTL field descriptions FIELD ECMD LOGIC 0 1 SYNASYN 0 1 AUDMODE 0 1 ENABRED 0 1 RWMD - DESCRIPTION Data is shifted in and stored when the next synchronization pattern is detected; (SYNASYN = 1 and AUDMODE = 0). Data flow stop just before next synchronization pattern. ECMD is set on a reset condition; (SYNASYN = 1). Synchronous/asynchronous selection; this controls the method by which data is started and stopped by the block decoder, only operates in data mode. Causes a `panic stop'. A partial frame will reside in current and subsequent buffers unless SIM_EOF is set then cleared; (ECMD = 1). Data is started and stopped on frame boundaries (on synchronization patterns). Data mode. Cleared on reset. Audio mode, where the bit clock is shifted to accommodate EIAJ format. HQRDY in INTRFLG follows HDRRDY in data mode and QFRMDRY in audio mode. Enable red book to data path; while in audio mode, this is equivalent to ECMD in the data mode. No asynchronous stop is provided in the audio mode. Data flow will stop when the next F1 C-flag is detected. Cleared on a reset condition. Red book data is input to buffer after the detection of the next F1 C-flag. This must be pulsed HIGH then LOW every 212 ms to prevent the watch-dog timer from resetting the SAA7390 and the drive. The length of the reset pulse is 967 s. If RWMD is set, the watch-dog timer is disabled. When set, the S2B UART transmitter output is held HIGH. When the pulse is HIGH then LOW, the block decoder begins to search for a synchronization pattern in the data bitstream. Once a synchronization pattern is found, MODE, MINS, SECS, and FRMS become valid. This provides a firmware reset to the frame sequencer and parts of the buffer manager. This would be required if an asynchronous stop of the data stream occurs. Pulsing this HIGH then LOW resets all counters and establishes a `beginning of frame' state. DCOACT in RDDSTAT must be LOW to allow SIM_EOF to have any effect. If SIM_EOF is set, no data or sub-code is stored in the buffer. R/W 7 R/W SIM_EOF 6 RSMD 5 BREAK 4 RWMD 3 2 1 0 ECMD ENABRED AUDMODE SYNASYN
BREAK RSMD
- -
SIM_EOF
-
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Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 41 Read status register: 0xF0C3; note 1 DATA BYTE MNEMONIC RDDSTAT Note R/W 7 R DCOTACT 6 BADQ 5 4 3 2 1
SAA7390
0 SYNCERR
QFRMRDY HDRRDY HDRERR CRCERR
DATERR
1. The information in register 0xF0C3 is a copy of the status byte written to the data buffer at the end of every frame. SYNCERR, DATERR and CRCERR are essentially unusable since they are valid only long enough to be written to the buffer. Table 42 RDDSTAT field descriptions FIELD SYNCERR DATERR CRCERR HDRERR LOGIC 0 0 0 0 1 HDRRDY - DESCRIPTION Good synchronization detected (valid for 120 ns at the end of a sector). Good data (valid for 120 ns at the end of a sector). Good CRC (valid for 120 ns at the end of a sector). Good header. If the automatic storage is selected, assertion of HDRERR inhibits data storage. EFAB during reception of header (valid while HDRRDY set). If the automatic storage is selected, assertion of HDRERR inhibits data storage. When set, a valid header is available. If the header is not read within a frame time, this remains set until the next synchronization pattern and will be set again when the next header arrives. It is cleared when any of the header bytes are read. This bit generates an interrupt to the microcontroller when in data mode. When set, all ten Q-channel bytes are received waiting to be read (BADQ is known). It is reset at the end of frame or when any of the Q-channel bytes are read. This bit generates an interrupt to the microcontroller when in audio mode. If Q-channel information failed CRC then BADQ is set. It is reset on next good CRC check or on end of frame if DCOACT is running. If DCOACT is not running (i.e. audio mode) BADQ is reset on next detection of sub-code gap. If AUTOSTR in WTDIR is selected, assertion of BADQ inhibits audio data storage. Set when data is being shifted an and stored in the buffer: this will remain HIGH for the entire transmission.
QFRMRDY
-
BADQ
-
DCOTACT
-
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
11 BUFFER MANAGER 11.1 Front-end to buffer manager interface
SAA7390
The buffer manager provides the remainder of the logic to write the data into the RAM and keep track of the frame addresses and offset addresses. This logic consists of a 12-bit frame offset counter FEOFF, for data and an 11-bit frame counter; this is a relative frame number and is not related to the CD-ROM frame number. Offset counters are also provided for the four other types of data. The other offset address generators are based on fixed addresses, and they will be loaded with the start address at the beginning of each frame. The five types of data from the front-end are loaded into the frame map as shown in Table 44.
The buffer manager interface to the front-end is write only with no handshaking. The front-end passes one byte of data and a write strobe to the buffer manager; this byte will be one of five types of data (see Table 44). The data byte is latched and the interface is given the highest priority thus no wait signal is required. The other signals passed from the front-end logic are an end-of-frame strobe (which is the same as the status byte write strobe), a software-generated reset pulse (used to reset the front-end counters), and a reset pulse for the Q-channel and sub-code offset counters. Table 43 Data types from the front-end START 0x000 0x930 0x940 0x9A0 0xBDE END 0x92F 0x93F 0x99F 0xAC5 0xBDE LENGTH 0x930 0x010 0x060 0x126 0x001
DATA TYPE header, data and parity Q-channel sub-channel error flags status byte
Initially the front-end frame counter and all of the offset counters are cleared by reset or loaded with the contents of FEFRM# when the last frame as specified by LASTFRM is filled; therefore FEFRM# should be loaded with the required starting frame number. FEFRM# will load the counter immediately if FEWBLK from BMFECTL is clear. If TDB_EN in BMFECLT is set then one frame may be read multiple times from memory; TDB selects the frame to be read and TDB_CNT determines the number of times the frame will be repeated. When this process is active, the frame counter will not increment until TDB_CNT reaches zero. LASTFRM establishes the limit of the frame memory. This register should be loaded with the required number of frames; the amount of memory used is 3 kbytes times the number of frames. The front-end frame address counter uses this value to determine the correct location to re-load the counter to the starting frame number, FEFRM#.
The frame counter and the frame data offset counter may be loaded by the microcontroller; this allows the starting frame number (via FEFRM#) to be modified by the microcontroller, and the frame data offset counter (FEFRMOFF) may be loaded for test purposes. Once the data load process starts, the offset counter (FEOFF) increments after each byte is written into memory. This process continues until an end-of-frame signal is received from the front-end logic. If an error occurs and the offset counter increments past the maximum 2352, an interrupt will be issued to the microcontroller.
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 44 Front-end frame offset: 0xF0E2, F0E3; note 1 DATA BYTE MNEMONIC FEFRMOFF FEFRMOFF Note R/W 7 R/W R/W - - - 6 5 4 - 3 2
SAA7390
1
0
OFFSET7 to OFFSET0 OFFSET11 to OFFSET8
1. This register allows the front-end frame offset counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is complete. Table 45 Front-end offset counter: 0xF09E, 0xF09F; note 1 DATA BYTE MNEMONIC FEOFF FEOFF Note 1. These registers access the actual counter for the front-end offset counter and therefore change rapidly during a transfer. The front-end frame offset counter is cleared after reset and after each frame is loaded into the buffer memory. Therefore, FEFRMOFF should not be loaded during normal operation. Table 46 Front-end offset counter: 0xF0E4, 0xF0E5; note 1 DATA BYTE MNEMONIC FEFRM# FEFRM# Note 1. This register allows the front-end frame number counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is completed. Table 47 Last frame number for storage: 0xF0F8, F0F9; note 1 DATA BYTE MNEMONIC LASTFRM LASTFRM Note 1. These registers are used by the buffer manager to set the top of frame storage memory (wrap point). Any memory past this point is available for general usage by the microcontroller. The outputs of the registers are used directly to control DRAM access cycles, and will affect any current DRAM cycle in progress. R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1 FRAME1 0 FRAME0 R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1 FRAME1 0 FRAME0 R/W 7 R/W R/W - - - 6 5 4 - 3 2 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8
FRAME10 to FRAME8
FRAME10 to FRAME8
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 48 Buffer manager front-end control: 0xF0E1 DATA BYTE MNEMONIC BMFECTL R/W 7 R/W - 6 - 5 - 4 - 3 STOP 2 FEWBLK
SAA7390
1 HW_BLK
0 TDB_EN
Table 49 BMFECTL field descriptions FIELD TDB_EN LOGIC - DESCRIPTION Track Descriptor Block (TDB) enable; default LOW. When set, this causes the buffer manager to continuously output the frame addressed by TBDL/TDBH for as many frames as programmed into TDB_CNT. TDB_CNT can be read and re-initialized while the TDB is being sent to the CDB2 to extend the count beyond 256. Host write block. If set HIGH, this bit will prevent a write to the host start frame number register (HOSTSFRM) for immediately changing the host frame counter (HOSTCFRM). The new value will be loaded at the next roll-over; a roll-over occurs when the host frame counter reaches the maximum frame number (LASTHOST) and is reloaded with the host start frame number. Front-end write block. If set HIGH, this bit will prevent a write to the front-end start frame number register (FEFRM#) from immediately changing the front-end counter. The new value will be loaded at the next roll-over; a roll-over occurs when the front-end frame counter reaches the maximum frame number (LASTFRM) and is reloaded with the front-end start frame number (FEFRM#). Automatic START control registers are selected. Automatic STOP control registers are selected. A page register is provided to allow the microcontroller to address the complete memory range in 32 kbytes pages. All microcontroller accesses to memory are single byte read or write cycles. All microcontroller accesses to memory will generate a wait state. If no other accesses to memory are in progress then a minimum wait state cycle will be generated. If, however, other cycles are in progress then the microcontroller is forced to wait until the lower priority access cycles finish and any high priority access cycles are completed. The worst case wait is four complete access cycles; a total of 20 clock cycles.
HW_BLK
-
FEWBLK
-
STOP
0 1
11.2
Microcontroller to buffer manager interface
The microcontroller interface allows the microcontroller to read or write any register or the frame store memory. Frame and offset registers are used to update the counters after the most significant byte has been loaded. Frame store memory is addressed using a frame number register controller by the microcontroller. Logic is provided to allow the frame number of the last complete frame received (LSTCMPFM) from the front-end to be read by the microcontroller for the purpose of setting the microcontroller frame address. Memory beyond the last frame number is available to the microcontroller using the microcontroller bottom 32 kbytes located at 0x0000 to 0x7FFF. The 4 kbytes segment at 0x8000 to 0x8FFF is used to address the current frame memory. Also, the next frame may be accessed at 0x9000 to 0x9FFF, and the current frame plus 2 may be accessed at 0xA000 to 0xAFFF.
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 50 Last complete frame number: 0xF0E6, F0E7; note 1 DATA BYTE MNEMONIC LSTCMPFM LSTCMPFM Note 1. This register provides the address of the last complete frame that was received. 11.3 ECC to buffer manager interface R/W 7 R R FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2
SAA7390
1 FRAME1
0 FRAME0
FRAME10 to FRAME8
The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides an offset address and uses a frame address programmed by the microcontroller, ECCFRM#. The logic can write a single byte or variable number of bytes. In the event of an access to a variable number of bytes, the ECC logic will assert the signal BURST and EREQ to indicate that a large number of cycles are requested. For each read or write cycle, the buffer manager will toggle EACK HIGH for one clock cycle to indicate that one byte of data has been read from or written to the memory. A single byte cycle will be the same with the exception that BURST will remain negated (LOW). In the event of a higher priority memory access request during a burst cycle, EACK will remain LOW for the duration of the higher priority access cycle. At the end of the higher priority access, the burst cycle will resume and EACK will again toggle HIGH after each read or write is completed. Table 51 ECC frame number address registers: 0xF0F4, F0F5; note 1 DATA BYTE MNEMONIC ECCFRM# ECCFRM# Note 1. These registers provide the frame number address for ECC access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the update will be delayed until the access is completed. R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1 FRAME1 0 FRAME0
FRAME10 to FRAME8
ECCFRM# is used to determine the frame address for all ECC operations. This register must be reloaded for each frame accessed by the ECC. 11.4 SCSI to buffer manager interface
controllers this bit is set LOW to select three clocks per CAS cycle. For faster host access, FAST should be asserted and the host burst cycle uses two clocks per CAS cycle. RD_BUF from HOSTMOD controls the direction of data flow to the buffer memory; this bit is kept LOW to allow reading of data from the DRAM buffer. If RD_BUF is asserted then host data will be written to the DRAM buffer. OFF_ADR from HOSTMOD is used to select between one and two offset mode for the host transfer. OFF_ADR LOW selects single offset mode in which one block of data is transferred for each frame of the buffer.
The host interface registers should be loaded prior to starting an host interface transfer. The HOSTMOD register should be loaded first. BYT/PAG and FAST from this register are used to control the type of DRAM access used by the host interface. If BYT/PAG is HIGH then burst mode access cycles are selected; multiple CAS access cycles are used to access data as fast as possible. FAST allows the speed of the burst cycle to be selected; for most host 1996 Jul 02 37
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
The transfer block is specified by registers HOSTOFFS and HOSTOFFE. For each frame, the transfer will start at the address specified by HOSTOFFS and continue until the address specified by HOSTOFFE is transferred. After each block is transferred, the frame address HOSTCFRM will be incremented and the transfer will continue with the same address block from the next frame. If OFF_ADR is set, then two blocks of data are transferred. In the two offset mode, both HOSTOFFS and HOSTOFFE are used to access two independent register pairs; for simplicity, these are called the A registers and the B registers. In this event, the transfer for each frame is a two step process. First, the offset block specified by HOSTOFFS-A and HOSTOFFE-A is transferred; the transfer address range is from HOSTOFFS-A to HOSTOFFE-A and includes both the start and end addresses. After the first offset block is transferred, the second offset block as specified by HOSTOFFS-B and HOSTOFFE-B is transferred. The frame address will not be incremented until after both offset blocks are transferred. Once both offset blocks are transferred, the frame address is incremented and again the two offset blocks are transferred for the next frame. Reading and writing of the A and the B registers is controlled by an automatic switching after the most significant bytes of the registers are written. After power-up or reset the pointer to the A registers will be selected. If the dual offset mode is selected, the A/B switch will be toggled when the most significant bytes of the registers are written; either the most significant bytes of
SAA7390
HOSTOFFS or HOSTOFFE. Any future reads or writes will access the B registers. The process of loading and reading the two host offset address pairs can be monitored and controlled by OFF_STR and OFF_END from HOSTMOD. Reading OFF_STR shows the status of the A/B switch for the HOSTOFFS-A/B registers; reading OFF_END shows the status of the A/B switch for the HOSTOFFE-A/B registers. A write to HOSTMOD with OFF_STR LOW will clear the A/B switch for the HOSTOFFS registers; a write to HOSTMOD with OFF_END LOW will clear the A/B switch for the HOSTOFFE registers. HOSTSFRM is used to determine the starting frame address for all host operations. The associated counter is automatically incremented after each frame, and wraps back onto HOSTSFRM when the last frame as specified by LSTFHOST is transferred. To update the host frame address counter, HOSTSFRM must be rewritten. The current host frame address is available by reading HOSTCFRM. The SCSIOFFS registers access either one or two register pairs as controlled by SCSIMOD. SCSIOFFS determines the starting offset address for a host transfer. The SCSIOFFE register accesses either one or two register pairs as controlled by SCSIMOD. SCSIOFFE determines the ending offset address for a host transfer. Remarks:
* If two offset pairs are used, the A start offset must be written last to ensure that the correct offset start address is loaded into the counter. * In the two offset mode, reading the register after loading is not possible due to the automatic switching feature; if the A offset pair is written, and the register pair is read, the B offset pair would be read. Table 52 Host interface offset counter: 0xF09C, F09D; note 1 DATA BYTE MNEMONIC HOFF HOFF Note 1. These addresses access the actual counter of the host interface offset counter and therefore rapidly change during host interface transfers. R/W 7 R/W R/W - - - 6 5 4 - 3 2 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 53 Host interface offset start register (A and B): 0xF0E8, F0E9; note 1 DATA BYTE MNEMONIC HOSTOFFS HOSTOFFS Note R/W 7 R/W R/W - - - 6 5 4 - 3 2
SAA7390
1
0
OFFSET7 to OFFSET0 OFFSET11 to OFFSET8
1. These registers, together with the offset end registers, allow full control over the number of frame bytes that will be transferred to the host interface port. Table 54 Host interface offset end register (A and B): 0xF0EA, F0EB; note 1 DATA BYTE MNEMONIC HOSTOFFE HOSTOFFE Note 1. These registers together with the offset start registers, allow full control over the number of frame bytes that will be transferred to the host interface port. Table 55 Host interface transfer start frame number: 0xF0EC, F0ED; note 1 DATA BYTE MNEMONIC HOSTSFRM HOSTSFRM Note 1. This register determines the starting frame number for a host interface transfer. The outputs of the registers are used to directly control DRAM access cycles, and will affect any current DRAM cycle in progress. The host interface frame pointer will wrap back to this point. Table 56 Host interface current transfer frame: 0xF0EE, F0EF; note 1 DATA BYTE MNEMONIC HOSTCFRM HOSTCFRM Note 1. This register allows the current host interface frame transfer number to be read. R/W 7 R R FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1 FRAME1 0 FRAME0 R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2 1 FRAME1 0 FRAME0 R/W 7 R/W R/W - - - 6 5 4 - 3 2 1 0 OFFSET7 to OFFSET0 OFFSET11 to OFFSET8
FRAME10 to FRAME8
FRAME10 to FRAME8
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 57 Ending frame number: 0xF0F2, F0F3 DATA BYTE MNEMONIC LSTFHOST LSTFHOST 11.5 R/W 7 R/W R/W FRAME7 - 6 FRAME6 - 5 FRAME5 - 4 FRAME4 - 3 FRAME3 - 2 FRAME2
SAA7390
1 FRAME1
0 FRAME0
FRAME10 to FRAME8
Miscellaneous buffer manager considerations
The following bandwidth limitation must be observed in normal operation: * Only 833 ns is available between each data write from the front-end at the maximum 8 times transfer rate. At the end of the frame, multiple front-end writes may stack up, so the microcontroller accesses to DRAM will be off (PCLK stopped) during the end of frame time. * After power-up or reset, the register DRAMSEL should be programmed first. Table 58 Selection/test mode: 0xF0FE; note 1 DATA BYTE MNEMONIC DRAMSEL Note 1. DRAMSEL1 and DRAMSEL0 are used to select the type of DRAM which is connected to the SAA7390. The test modes are also defined by the DRAMSEL register. Table 59 DRAMSEL field descriptions FIELD DRAMSEL1 DRAMSEL0 LOGIC 00 01 10 11 REFRATE RES_TEST0 RES_TEST1 RES_TEST2 TEST 0 1 - - - - 256 kbytes 1 Mbyte not applicable 4 Mbytes normal refresh rate double refresh rate; set HIGH if clock is running at 12 normal rate, or 16.9 MHz reserved for test; setting this HIGH enables the DRAM access test, a write to INTRMSK sets a front-end access test, and a write to PAGEREG sets a test ECC access reserved for test; setting this HIGH enables the switch multiplexer control reserved for test; setting this HIGH enables the interrupt test, a write to PAGEREG will set interrupts test mode; this bit must be set to enable the test modes, also, read back of any of the test bits is gated by this bit DESCRIPTION R/W 7 R/W TEST 6 5 4 3 2 1 0 - RES_TEST2 to RES_TEST0 REFRATE DRAMSEL1 DRAMSEL0
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 60 Automatic start and stop control functions (same address): 0xF0C5, F0C6 and F0C7 DATA BYTE MNEMONIC STRTMIN STRTSEC STRTFRM STOPCNT STOPCNT R/W 7 R/W R/W R/W R/W R/W - - - 6 5 4 3 2 1
SAA7390
0
MINUTE7 to MINUTE0 SECOND7 to SECOND0 FRAME7 to FRAME0 COUNT7 to COUNT0 - - COUNT10 to COUNT8
The multiplexing between the start and stop registers is achieved by programming STOP in BMFECTL. If STOP is clear then STRTMIN, STRTSEC and STRTFRM are accessible, otherwise STOPCNT may be accessed. These registers contain the start address (MSF) and the stop count for the automatic read control function. When the block decoders header or registers equal the start address, the front-end will start to send data to the buffer manager until the down counter STOPCNT decrements to zero, at which time the data flow stops. The header registers are selected then AUDMODE in FECTL is LOW, otherwise the Q registers are selected; the latter event is used for loading audio data. The start registers are selected when FEWBLK in BMFECLT is LOW, otherwise the STOPCNT registers are selected. The start registers should be programmed to `Header 1'. If EFAB (C2 failure) is asserted while the header is shifting in, the data flow will not start. The same is true for BADQ (Q channel CRC failure) used in the audio mode. 11.6 Host interface related registers
In the 53CF9X series of SCSI controllers, some registers are read only and others are write only. These share the same address and the multiplexing between the two depends on the read or write select. The address mapping is: 0xF0A4 to 0xF0A7, 0xF0AC to 0xF0AF, 0xF0B4 to 0xF0B7, 0xF0BC to 0xF0BF maps onto the external interface device address range 0x00 to 0x0F respectively. 11.7 CDB2 related registers
This section outlines the registers which are related to the modified CDB2 block encoder. Figure 13 shows a functional block diagram for the CDB2. Figure 14 explains the generation of header and sub-header information.
The SAA7390 provides a 16 address wide pass through mechanism to communicate to an external SCSI or ATAPI interface device. Supported devices include the 53CF9X series of SCSI controllers and the Wapiti ATAPI controller. The register definitions for the external device can be found in the corresponding data sheet.
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
microcontroller handbook, full pagewidth access MICROCONTROLLER INTERFACE
ROM
RAM
ERROR CORRECTION CODE GENERATION
TIMER AND CONTROL LOGIC
BLOCK COUNTER AND HEADER GENERATION
SCRAMBLER
BYTE SWAP AND I2S INTERFACE
I2S output
DATA INTERFACE
ERROR DETECTION CODE GENERATION
MGD620
data cource
Fig.13 Functional block diagram for the CDB2.
handbook, full pagewidth
MICROCONTROLLER INTERFACE
registers
CMD
STS
registers
BCH
BCL
registers
BCH
BCL
registers
MIN
SEC
FRM MODE
registers
MIN
SEC
FRM
registers data
FILN
CHAN SUBM DTYP BCM MUX output
MGD621
Fig.14 Generation of the header and sub-header information.
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 61 Interrupt mask register: 0xF0CE; note 1 DATA BYTE MNEMONIC CMSK Note R/W 7 R/W - 6 - 5 4 3 ACKINT 2 HEF
SAA7390
1 ACA
0 LBT
EOFMSK COM_SYS
1. Register 0xF0CE contains the mask bits for the various SAA7390 specific interrupts. Setting a mask bit HIGH enables the interrupt. The register is cleared to all zeros after reset. The definitions of the bit fields of CMSK are given in Table .63. Table 62 CMSK field descriptions FIELD LBT ACA HEF ACKINT COM_SYS EOFMSK block counter equals zero access allowed DMA to CDB2 under-run interrupt from serial communication with basic engine COMSYNC/SYSSYNC clock interrupt end of frame interrupt generated by CDB2 when writing to the disc in audio or data mode DESCRIPTION
Table 63 Command register: 0xF0D1 DATA BYTE MNEMONIC CCMD R/W 7 R/W SRS 6 BPE 5 ACT 4 DRQ 3 NHD 2 CDI 1 SBH 0 ED2
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 64 CCMD field descriptions FIELD ED2 SBH CDI NHD DRQ ACT BPE SRS LOGIC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1. Only has effect in CDI mode. 2. Latched on rising edge of ACA. Table 65 Status register: 0xF0D2 DATA BYTE MNEMONIC CSTS R/W 7 R ATT 6 HEF 5 LBT 4 ACA 3 RDY 2 NRQ DESCRIPTION no EDC in CDI, Form 2; zeros replace CRC; note 1 EDC is performed in CDI, Form 2; note 1 sub-header retrieved from sub-header register; note 2 sub-header retrieved from host data; note 2 CD-ROM mode; note 2 CDI mode; note 2 header calculated internally; note 2 header supplied by host; note 2 requests to host are enabled; note 2
SAA7390
requests to host are disabled; this is now synchronous with the end-of-frame signal; note 2 continue transmission; note 2 stop transmission during next block; note 2 bypass disabled; note 2 bypass enabled; this is now synchronous with the end-of-frame signal; note 2 normal operation soft reset to CDB2
1 SAR
0 -
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 66 CSTS field descriptions FIELD SAR NRQ(1) RDY(2) ACA LBT HEF ATT(4) LOGIC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1. Normally NRQ is LOW during synchronization, header and EDC/ECC transmission. 2. RDY is set after command bit ACT is pulled LOW. 3. This is a fatal error which can be rectified only by restarting CDB2. 4. Interrupt sources are ACA = logic 1, LBT = logic 0 and HEF = logic 1. Table 67 Block count registers: 0xF0D3 and 0xF0D4; note 1 DATA BYTE MNEMONIC CBCL CBCH Note R/W 7 R/W R/W 6 5 4 3 2 status already read no request to host will be issued requests to host will be issued data block transmission is in progress data transmission is ceased access to CDB2 is denied access to CDB2 is allowed state of block counter has reached zero block counter is non zero no error has occurred during communication with the host an error has occurred in the host communication process; note 3 interrupt to microcontroller is asserted no pending interrupts DESCRIPTION status not ready yet during this block; SAR cleared on each new block
SAA7390
1
0
BLOCKCOUNT7 to BLOCKCOUNT0 BLOCKCOUNT15 to BLOCKCOUNT8
1. This is a 16-bit down counter which should be programmed with the; number of blocks - 1. As soon as the count value reaches zero, LBT is cleared and ATT is pulled LOW. LBT remains active for 13.3 ms at single speed record. Note that the counter continue to decrement. New programmed information is used at the start of the next block. Table 68 Header containing MSF address and mode: 0xF0D5, F0D6, F0D7 and F0DB DATA BYTE MNEMONIC CMDE CMIN CSEC CFRM R/W 7 R/W R/W R/W R/W - 6 - 5 - 4 - 3 - 2 - 1 MODE1 0 MODE0
MINUTES7 to MINUTES0 SECONDS7 to SECONDS0 FRAME7 to FRAME0
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
Automatic header generation is implemented in the CDB2. Once the initial header value is loaded, the header is incremented and added to the user data in accordance with the Yellow book rules. When the information is written into the header registers, this is used by the CDB2 at the start of the next frame. MODE1 and MODE0 specifies the CD-ROM mode used, even when NHD = logic 1. Table 69 Sub-header information fields: 0xF0DC, F0DD, F0DE and F0DF; note 1 DATA BYTE MNEMONIC CFN CCHAN CSMD CDTB Note 1. These form the CDB2 sub-header information, comprising of the file number, channel, mode and data type. Table 70 Test register for CDB2: 0xF0D8; note 1 DATA BYTE MNEMONIC CTST Note 1. This register is strictly for use by the manufacturer. Setting any bits will result in undefined operation. Table 71 Control register for CDB2: 0xF0D9 DATA BYTE MNEMONIC CCTL R/W 7 R/W HSTSH 6 HSH 5 CDB2ECC 4 - 3 - 2 - 1 0 0 RSTA R/W 7 W - 6 - 5 SYN_PD 4 S_CPSEL 3 S_FDBK 2 S_OUTEN 1 TEST1 0 TEST0 R/W 7 R/W R/W R/W R/W 6 5 4 3 2 1 0 FILENUMBER7 to FILENUMBER0 CHANNEL7 to CHANNEL0 SUBMODE7 to SUBMODE0 DATATYPE7 to DATATYPE0
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
Table 72 CCTL field descriptions FIELD RSTA CDB2ECC HSH(1) HSTSH(2) 0 1 0 1 LOGIC DESCRIPTION to reset CDB2, first set RSTA HIGH then LOW
SAA7390
when set, enables the ECC RAM to be used by the CDB2 during encoding of ECC parity header supplied from CDB2 header supplied by host sub-header supplied from CDB2 sub-header supplied by host
Table 73 Status register for CDB2: 0xF0DA DATA BYTE MNEMONIC CSTAT R/W 7 R 6 5 4 3 2 - 1 - 0 EOFCDB2 COM/SYS COMSYNC SYSSYNC ACKINT COMACK
Table 74 CCTL field descriptions FIELD EOFCDB2 COMACK DESCRIPTION end of frame interrupt from CDB2; generated in both bypass and CD-ROM modes Acknowledge signal from the basic engine indicating reception of a byte in its register. The HIGH-to-LOW transition of this signal indicates `ready to receive' and generates an interrupt to the microcontroller. indicates a HIGH-to-LOW transition on COMACK; this status is not affected by masking bits one of the serial synchronization signals one of the serial synchronization signals combination of the SYSSYNC and COMSYNC interrupts; control of selection is via SC_CTL
ACKINT SYSSYNC COMSYNC COM/SYS
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
12 FRAME BUFFER ORGANIZATION The break-down of the 3 kbytes frame buffer is described in this section. Table 75 Frame buffer organization DECIMAL START 0 12 16 2064 2068 2076 2248 2352 2368 2464 2758 2762 2934 3038 END 11 15 2063 2067 2075 2247 2351 2367 2463 2757 2761 2933 3037 3038 LEN 12 4 2048 4 8 172 104 16 96 294 4 172 104 1 START 000 00C 010 810 814 81C 8C8 930 940 9A0 AC6 ACA B76 BDE HEXADECIMAL
SAA7390
DATA END 00B 00F 80F 813 81B 8C7 92F 93F 99F AC5 AC9 B75 BDD BDE LEN 00C 004 800 004 008 0AC 068 010 060 126 004 0AC 068 001 synchronization field header frame data CRC parity padding P parity Q parity Q channel sub-channel error flags CRC remainder P syndromes Q syndromes status
Table 76 ECC RAM organization BYTE NUMBER DEC 000 204 208 340 344 564 568 572 576 580 584 588 HEX 3 000 0CC 0D0 154 158 234 238 23C 240 244 248 588 psyn[00].s1 psyn[51].s1 psyn[52].s1 psyn[85].s1 flags[071] flags[291] unused[1] crc_rem[3] header[3] ecc_reg[03] ecc_reg[07] ecc_reg[11] 2 psyn[00].s0 psyn[51].s0 psyn[52].s0 psyn[85].s0 flage[070] flage[290] unused[0] crc_rem[2] header[2] ecc_reg[02] ecc_reg[06] ecc_reg[10] 1 qsyn[00].s1 qsyn[51].s1 flags[001] flags[067] flags[069] flags[289] flags[293] crc_rem[1] header[1] ecc_reg[01] ecc_reg[05] ecc_reg[09] 0 qsyn[00].s0 qsyn[51].s0 flags[000] flags[066] flags[068] flags[288] flags[292] crc_rem[0] header[0] ecc_reg[00] ecc_reg[04] ecc_reg[08]
1996 Jul 02
48
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
13 SUMMARY OF CONTROL REGISTER MAP Table 77 Control register map for the SAA7390 ADDRESS F084 F085 F086 F08E F08F F091 F092 F093 F094 F095 F096 F097 F09A F09B F09C F09D F09E F09F F0A1 F0A2 F0A3 F0A4 F0A5 F0A6 F0A7 F0A9 F0AA F0AB F0AC F0AD F0AE F0AF F0B1 F0B2 F0B3 F0B4 F0B5 F0B6 MNEMONIC QZERO ECCCTL ECCSTAT NUM_COR TDB_CNT CLKSEL HDRMODE HDRFRM QFRM QMIN TDB TDB HDRSEC HDRMIN HOFF HOFF FEOFF FEOFF WTS2B RDS2B S2BSTAT HOSTPASS HOSTPASS HOSTPASS HOSTPASS QTNO QMODE QAMIN HOSTPASS HOSTPASS HOSTPASS HOSTPASS QASEC QAFRM - HOSTPASS HOSTPASS HOSTPASS READ/WRITE R R/W R R R/W W R R R R R/W R/W R R R R R R W R R R/W R/W R/W R/W R R R R/W R/W R/W R/W R R - R/W R/W R/W Q channel zero byte ECC control register ECC status register ECC register for the number of corrections track descriptor count start the clock synthesizer (doubler) header mode byte from block decoder header frame byte from block decoder Q channel frame (track relative) Q channel minutes (track relative) track descriptor block frame number low track descriptor block frame number high header seconds byte from block decoder header minutes byte from block decoder host interface offset register low host interface offset register high front-end offset register low front-end offset register high S2B UART transmit buffer S2B UART receive buffer S2B UART status register DESCRIPTION
SAA7390
interface device pass through register address 0x00 interface device pass through register address 0x01 interface device pass through register address 0x02 interface device pass through register address 0x03 Q channel track number Q channel mode number Q channel minutes number (absolute) interface device pass through register address 0x04 interface device pass through register address 0x05 interface device pass through register address 0x06 interface device pass through register address 0x07 Q channel seconds (absolute) Q channel frames (absolute) not connected interface device pass through register address 0x08 interface device pass through register address 0x09 interface device pass through register address 0x0A
1996 Jul 02
49
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
ADDRESS F0B7 F0B9 F0BA F0BB F0BC F0BD F0BE F0BF F0C0 F0C1 F0C2 F0C3 F0C4 F0C5 F0C6 F0C6 F0C7 F0C7 F0C9 F0CE F0CF F0D1 F0D2 F0D3 F0D4 F0D5 F0D6 F0D7 F0D8 F0D9 F0DA F0DB F0DC F0DD F0DE F0DF F0E1 F0E2 F0E3 F0E4 F0E5 1996 Jul 02 MNEMONIC HOSTPASS WTGCTL RDSW FECTL HOSTPASS HOSTPASS HOSTPASS HOSTPASS BRGSEL WTDIR GPIOCTL RDDSTAT SERCOM STRTMIN STRTSEC STOPCNT STRTFRM STOPCNT RDJMPRS CMSK QINDX CCMD CSTS CBCH CBCL CMIN CSEC CFRM CTST CCTL CSTAT CMDE CFN CCHAN CSMD CDTB BMFECTL FEFRMOFF FEFRMOFF FEFRM# FEFRM# READ/WRITE R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R/W R/W R/W R/W W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION
SAA7390
interface device pass through register address 0x0B GLIC control registers (audio control) drive control switches register front-end control register interface device pass through register address 0x0C interface device pass through register address 0x0D interface device pass through register address 0x0E interface device pass through register address 0x0F baud rate generator select register SAA7390-host interface direction plus audio mode control general purpose bits control register data status register SAA7390: basic engine communications port start minutes (automatic control) start seconds (automatic control) stop count low byte (automatic control) start frame (automatic control) stop count high byte (automatic control) option jumper register (attached to DRAM data bus) CDB2 interrupt mask register Q channel index (track relative) CDB2 command register CDB2 status register CDB2 block counter high CDB2 block counter low CDB2 header minutes register CDB2 header seconds register CDB2 header frame register test register for CDB2 block control register for CDB2 block status register for CDB2 block CDB2 header mode register CDB2 file number register CDB2 channel number register CDB2 sub-mode byte register CDB2 data type byte register buffer manager front-end control front-end 8 LSBs; frame offset front-end 4 MSBs; frame offset (bit 0 to bit 3) front-end 8 LSBs of the frame front-end 3 MSBs of the frame (bit 0 to bit 2) 50
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
ADDRESS F0E6 F0E7 F0E8 F0E9 F0EA F0EB F0EC F0ED F0EE F0EF F0F1 F0F2 F0F3 F0F4 F0F5 F0F6 F0F7 F0F8 F0F9 F0FA F0FB F0FC F0FD F0FE F0FF MNEMONIC LSTCMPFM LSTCMPFM HOSTOFFS HOSTOFFS HOSTOFFE HOSTOFFE HOSTSFRM HOSTSFRM HOSTCFRM HOSTCFRM SC_CTL LSTFHOST LSTFHOST ECCFRM# ECCFRM# MICFRM# MICFRM# LASTFRM LASTFRM QSEC INTRMSK INTRFLG HOSTMOD DRAMSEL PAGEREG READ/WRITE R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W DESCRIPTION 8 LSBs; last complete frame number
SAA7390
3 MSBs; last complete frame number (bit 0 to bit 2) host interface 8 LSBs; offset start (A and B) host interface 4 MSBs; offset start (bit 0 to bit 3) host interface 8 LSBs; offset end (A and B) host interface 4 MSBs; offset end (bit 0 to bit 3) host interface 8 LSBs; start transfer frame number host interface 3 MSBs; start frame number (bit 0 to bit 2) host interface 8 LSBs; current frame number host interface 3 MSBs; current frame number (bit 0 to bit 2) serial communication control last frame host interface LOW last frame host interface HIGH ECC 8 LSBs; frame number (frame address) ECC 3 MSBs; frame number (bit 0 to bit 2) microcontroller 8 LSBs; frame number (frame address) microcontroller 3 MSBs; frame number (bit 0 to bit 2) last frame number for storage 8 LSBs last frame number 3 MSBs (bit 0 to bit 2) Q channel seconds (track relative) interrupt mask register interrupt flag register host interface mode control DRAM selection/test mode register. 80C32 linear address page register
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Vi(max) Vo Tstg digital supply voltage maximum input voltage on any pin output voltage on any output storage temperature PARAMETER MIN. -0.5 VSS - 0.5 -0.5 -55 +7
SAA7390
MAX. VDD + 0.5 +7 +150
UNIT V V V C
15 OPERATING CHARACTERISTICS 15.1 I2S-bus timing; data mode VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I2S-bus timing (single speed x n); see Fig.15 and note 1 CLOCK INPUT: CLAB Tcy output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs INPUTS: DAAB, WSAB AND EFAB tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. The I2S-bus timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
1996 Jul 02
52
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.2 EIAJ timing; audio mode VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7390
MAX.
UNIT
EIAJ timing (single speed x n); see Fig.16 and note 1 CLOCK INPUT: CLAB Tcy output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs INPUTS: DAAB, WSAB AND EFAB tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. The EIAJ timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
CLAB
DAAB
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
WSAB
left
right
EFAB (error flags)
left LSB valid
right MSB valid clock period Tcy tCL tCH
right LSB valid
VDD - 0.8V CLAB 0.8 V th DAAB WSAB EFAB tsu VDD - 0.8 V 0.8 V
MGE399
Fig.15 I2S-bus timing diagram.
handbook, full pagewidth
CLAB
DAAB
1
0
17
16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
WSAB EFAB clock period Tcy
left
right
tCL
tCH VDD - 0.8V
CLAB 0.8 V th DAAB WSAB EFAB tsu VDD - 0.8 V 0.8 V
MGE400
Fig.16 EIAJ timing diagram.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.3 R-W timing (see Fig.17) 15.4 C-flag timing (see Fig.18)
SAA7390
The data from sub-code R-W may be read via the V4 pin from the CD-decoder (SAA7372) and has a format similar to RS232. The sub-code synchronization word is formatted by a pause of 200 s minimum. Each sub-code byte starts with a logic 1 followed by seven bits (Q to W). The gap between bytes is variable between 1.3 and 90 s.
A 1-bit flag signal is input to the CFLAG pin. This signal shows the status of the error corrector and interpolator and is updated every frame.
handbook, full pagewidth
200 s min W96 1
11.3 s Q1 R1 S1 T1 U1 V1 W1
11.3 s min 90 s max 1
MGE401
Fig.17 Sub-code formatting and timing from the V4 pin.
handbook, full pagewidth
11.3 s F1 F2 F3 F4 F5 F6 F7
45.4 s (nominal speed)
MGE402
Fig.18 C-flag output timing.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.5 S2B interface timing
SAA7390
A data frame is proceeded by a start-bit (active LOW), followed by the actual data byte, and again followed by a parity bit (even parity), and a stop bit (active HIGH), see Fig.20. In total, eleven bits per frame are incorporated. The interface is full duplex, meaning data frames may be transmitted and received simultaneously. The bit-rate is selectable: 187.5 kbits/s with a 2.6% error 62.5 kbits/s with a 0.4% error 31.25 kbits/s with a 0.4% error.
The S2B serial interface consists of four lines (see Fig.19): Transmit data (TXD) Receive data (RXD) Data path ready to accept data; active LOW (CPR) Basic engine ready to accept data; active LOW (SPR). These are used for communication. TXD and CPR for sending acknowledges and information data to the data path and RXD and SPR for receiving commands and parameters from the data path. The data is transferred frame-wise and asynchronously.
data path handbook, halfpage RXD CPR TXD SPR sequoia
basic engine TXD CPR RXD SPR
MGE403
Fig.19 S2B interface.
handbook, halfpage
TXD
S0
0
1
2
3
4
5
6
7
P S1
CPR
MGE404
Fig.20 S2B Timing.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.6 SPI interface timing
SAA7390
The control interface channel is implemented as a bidirectional, synchronous, high-speed serial link, having the following advantages: * The Q sub-code and header data can be coupled (synchronized) * The user part has real time access of the Q sub-code information * The user part has full control over the CD-R engines mode of operation, for example synchronous stop while recording * High speed data transfers are possible; up to 2 Mbits/s for the microcontroller in slave mode.
The control communication between the CD-R engine and the interface module is based on data blocks that are swapped in the same cycle. The control communication channel is byte and message synchronous. Byte synchronization is realized with an acknowledge after each byte that is transferred. Message synchronization is ensured through resetting the serial shift register after each communication synchronization pulse. This is to detect the start of the next data block even if a time-out or bit-slip occurs. This control interface is used for the exchange of: * Sub-code data * Commands with parameters * Status information. Table 78 SPI timing parameters SYMBOL Tcy tCH tCL tsu th td serial clock cycle time serial clock HIGH time Serial clock LOW time serial input data set-up time to COM_CLK serial input data hold time from COM_CLK serial output delay after COM_CLK PARAMETER
MIN. 500 210 210 80 80 0 - - - - -
MAX. ns ns ns ns ns ns
UNIT
150
handbook, full pagewidth
COMM_SYNC
engine data available
COM_ACK
user data available
COM_CLK
MGE523
Fig.21 Serial communication timing and synchronization.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
serial data in 30 to 700 s acknowledge
MGE524
30 to 700 s
Fig.22 Acknowledge signal timing.
handbook, full pagewidth
tCL COM_CLK Tcy COM_IN
tCH
tsu th
td COM_OUT
MGE525
Fig.23 Synchronous serial communication channel timing.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.6.1 RELATIONSHIP BETWEEN COMMUNICATION AND SYSTEM SYNCHRONIZATION
SAA7390
The system synchronization line (SYS_SYNC) is locked on a hardware generated frame synchronization; the decoders sub-code, the ATIP and the encoders synchronization signals. The communication synchronization line (COM_SYNC) has the same frequency as SYS_SYNC, except for four-times speed operation, where it is down-scaled with a factor 3. Table 80 provides a representation between the speed and synchronization lines. Table 79 Relationship of synchronization line frequency and speed. SPEED (ms) SIGNAL n=1 SYS_SYNC (full period) SYS_SYNC (half period) COM_SYNC (half period) 13.3 6.6 6.6 n=2 6.6 3.3 3.3 n=4 3.3 1.66 5.0 n=6 2.2 1.1 3.3
handbook, full pagewidth
decoder interrupt
ATIP sync interrupt
encoder interrupt
COM_SYNC
SYS_SYNC
MGE526
Fig.24 Phase relationship of COM_SYNC and SYS_SYNC (n = 1, n = 2).
handbook, full pagewidth
decoder interrupt
COM_SYNC
SYS_SYNC
MGE527
Fig.25 Phase relationship of COM_SYNC and SYS_SYNC (n = 4).
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.7 Microprocessor interface VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER MIN. - - - - - 65 - 30 130 6 - - 135 - 70 235 260 115 - - - 0 40 MAX.
SAA7390
UNIT
Microprocessor timing; see Figs 26, 27 and 28 tLHLL tAVLL tLLAX tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid input instruction Input instruction hold after PSEN Input instruction float after PSEN address to valid input instruction PSEN low to address float UC_RD pulse width UC_WR pulse width UC_RD LOW to valid input data data hold after UC_RD data float after UC_RD ALE LOW to valid input data address to valid input data ALE LOW to UC_RD or UC_WR LOW address LOW to UC_RD or UC_WR LOW data valid to UC_WR transition data hold after UC_WR UC_RD LOW to address float UC_RD or UC_WR LOW to ALE HIGH 60 15 35 25 80 - 0 - - - 180 180 - 0 - - - 90 115 20 20 - 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
tLHLL ALE tAVLL tLLPL tPLPH tPLIV
PSEN tLLAX tPLAZ LA7 to LA0 tAVIV A15 to A8
MGE528
tPXIZ tPXIX
Fig.26 External program memory read cycle.
handbook, full pagewidth
ALE tWHLH PSEN tLLDV tLLWL tRLRH
UC_RD tLLAX tAVLL UC_AD7 to UC_AD0 tAVWL tAVDV UC_A15 to UC_A8
MGE529
tRHDZ tRLVD
Fig.27 External data memory read cycle.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
ALE tWHLH
PSEN tLLWL UC_WR tLLAX tAVLL tQVWX UC_AD7 to UC_AD0 tAVWL UC_A15 to UC_A8 tWHQX tRLRH
MGE530
Fig.28 External data memory write cycle.
1996 Jul 02
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Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.8 Host interface
SAA7390
15.8.1 REGISTER INTERFACE VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER MIN. - - - - - - - 40 25 25 25 - - - - - - - 40 25 25 25 25 MAX. UNIT
Read cycle timing; see Fig.29; note 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Note 1. These timings are taken form the 53CF90; the 53CD92A/B timings are slightly different. address set-up time to HOSTSEL LOW address hold time from HOSTSEL LOW HOSTSEL HIGH to HOSTSEL LOW HOSTSEL LOW to HOSTRD LOW HOSTRD pulse width HOSTRD HIGH to HOSTSEL HIGH HOSTRD HIGH to HOSTSEL LOW HOSTSEL LOW to data valid HOSTRD LOW to data valid HOSTSEL HIGH to data release HOSTRD HIGH to data release 0 50 40 0 25 0 40 0 0 2 2 ns ns ns ns ns ns ns ns ns ns ns
Write cycle timing; see Fig.30; note 1 address set-up time to HOSTSEL LOW address hold time from HOSTSEL LOW HOSTSEL HIGH to HOSTSEL LOW HOSTSEL LOW to HOSTWR LOW HOSTWR pulse width HOSTWR HIGH to HOSTSEL HIGH HOSTWR HIGH to HOSTSEL LOW HOSTWR HIGH to HOSTWR LOW data set-up time to HOSTWR HIGH data hold time from HOSTWR HIGH data set-up time to HOSTSEL HIGH data hold time from HOSTSEL HIGH 0 50 40 0 25 0 40 40 8 0 10 35 ns ns ns ns ns ns ns ns ns ns ns ns
1996 Jul 02
63
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
UC_AD3 to UC_AD0 t1 HOSTSEL t5 HOSTRD t7 t4 UC_AD7 to UC_AD0 t8 t11
MGE531
t2
t6
t3
t9
t10
Fig.29 Register read cycle timing.
handbook, full pagewidth
UC_AD3 to UC_AD0 t1 HOSTSEL t7 t8 t2 t6 t3
t5 HOSTWR t4 UC_AD7 to UC_AD0 t9 t11 t10 t12
MGE532
Fig.30 Register write cycle timing.
1996 Jul 02
64
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.8.2 DMA INTERFACE TIMING VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL DMA read cycle timing; see Fig.31 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Note 1. tCS + 30 -t3 and tCP; where tCS is the synchronization latency and tCP is the clock period. DACK LOW to DREQ LOW DACK HIGH to DREQ HIGH DACK HIGH to DACK LOW DACK pulse width DACK LOW to DACK LOW DACK HIGH to DACK HIGH DACK LOW to HOSTRD LOW HOSTRD pulse width HOSTRD HIGH to DACK HIGH DACK HIGH to data valid DACK LOW to data valid HOSTRD LOW to data valid DACK HIGH to data release HOSTRD HIGH to data release - - 12 35 75 note 1 0 t12 0 - - - 2 2 - - 12 35 75 note 1 0 30 0 30 8 0 10 10 20 20 - - - - - - - 30 25 25 25 25 PARAMETER MIN. MAX.
SAA7390
UNIT
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DMA write cycle timing; see Fig.32 DACK LOW to DREQ LOW DACK HIGH to DREQ HIGH DACK HIGH to DACK LOW DACK pulse width DACK LOW to DACK LOW DACK HIGH to DACK HIGH DACK LOW to HOSTWR LOW HOSTWR pulse width HOSTWR HIGH to DACK HIGH HOSTWR HIGH to HOSTWR HIGH data set-up time to HOSTWR HIGH data hold time from HOSTWR HIGH data set-up time to DACK HIGH data hold time from DACK HIGH 20 20 - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Jul 02
65
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
dbook, full pagewidth
DREQ t6 t1 t5 t4 DACK t7 HOSTRD t13 t12 SD7 to SD0
MGE533
t2
t8
t9
t3
t14
t11 t10
Fig.31 DMA read cycle timing.
handbook, full pagewidth
DREQ t6 t1 t5 t4 DACK t7 HOSTWR t10 t11 t12 t8 t9 t3 t2
SD7 to SD0 t13
MGE534
t14
Fig.32 DMA write cycle timing.
1996 Jul 02
66
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
15.9 DRAM interface (the SAA7390 is designed to operate with standard 70 ns DRAMs) VDD = 4.75 to 5.25 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER - 55 0 0 - 15 20 15 3 10 - 5 70 5 20 15 55 0 3 40 n/a(1) - 15 10 70 70 35 130 20 0 0 - 50 0 0 20 n/a(1) MIN. MAX.
SAA7390
UNIT
DRAM interface timing; see Figs 33 to 37 tacc;CA thCA;RAS tsu;CA tsu;RA tacc;CAS th;CA tW;CAS th;CAS tCASLZ tpCAS tacc;pCAS tpCAS;RAS th;CAS tsu;CAS twCASL th;DAT thDAT;RAS tsu;DAT td;OFF tcy;FPR/W tcy;FPR-W tacc;RAS tdRAS;CA th;RA tW;RAS tW;RASFP tCA;RASL tcy;R/W tdRAS;CAS tsu;R thrR;CAS tREF tpRAS tpRAS;CAS thr;RAS th;RAS tcy;R-W access time from column address column address hold time from RAS column address set-up time row address set-up time access time from CAS column address hold time CAS pulse width CAS hold time (CBR refresh) CAS to output in low impedance CAS precharge time access time from CAS precharge CAS to RAS precharge time CAS hold time CAS set-up time (CBR refresh) write command to CAS lead time data input hold time data input hold time from RAS data input set-up time output buffer turn off delay fast page mode read or write cycle time fast page mode read-write cycle time access time from RAS RAS to column address delay time row address hold time RAS pulse width RAS pulse width (fast page mode) column address to RAS lead time random read or write cycle time RAS to CAS delay time read command set-up time read command hold time (referenced to CAS) refresh period RAS precharge time RAS to CAS precharge time read command hold time (referenced to RAS) RAS hold time read-write cycle time 35 - - - 20 - 10000 - - - 40 - - - - - - - 20 - - 70 35 - 10000 100000 - - 50 - - 32 - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1996 Jul 02
67
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SYMBOL tRASL;W ttrans thW thW;RAS tsu;WE tW;W th;WE tsu;WE Note 1. Not applicable. PARAMETER write command to RAS lead time transition time (rise or fall) write command hold time write command hold time (referenced to RAS) WE command set-up time write command pulse width WE hold time (CBR refresh) WE set-up time (CBR refresh) 20 3 15 55 0 15 10 10 MIN. - 50 - - - - - - MAX.
SAA7390
UNIT ns ns ns ns ns ns ns ns
handbook, full pagewidth
tcy;R/W tW;RAS tpRAS
RAS th;CAS tpCAS;RAS tdRAS;CAS th;RAS tW;CAS
CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA th;CA tCA;RASL
ADDRESS
ROW
COLUMN tacc;CA tacc;RAS tacc;CAS tCASLZ
ROW
td;OFF
DATA
MGE412
Fig.33 DRAM read cycle.
1996 Jul 02
68
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
tcy;R/W tW;RAS tpRAS
RAS th;CAS tpCAS;RAS tdRAS;CAS th;RAS tW;CAS
CAS thCA;RAS tdRAS;CA tsu;RA th;RA tsu;CA th;CA tCA;RASL
ADDRESS
ROW
COLUMN thDAT;RAS th;DAT
ROW
tsu;DAT
DATA
MGE413
Fig.34 DRAM early write cycle.
1996 Jul 02
69
andbook, full pagewidth
1996 Jul 02
tW;RASFP th;CAS tcy;FPR/W tW;CAS tpCAS tW;CAS tpCAS th;RAS tW;CAS
Philips Semiconductors
RAS
tpCAS;RAS
tdRAS;CAS
CAS
High performance Compact Disc-Recordable (CD-R) controller
thCA;RAS tdRAS;CA th;CA tsu;CA tsu;CA th;CA
tsu;RA
th;RA
tsu;CA
tCA;RASL th;CA
70
COLUMN tacc;CA tacc;pCAS tacc;CAS td;OFF tCASLZ tacc;CAS tCASLZ tacc;pCAS td;OFF tacc;CA COLUMN COLUMN tacc;CA tacc;pCAS tacc;CAS tCASLZ td;OFF
MGE414
ADDRESS
ROW
DATA
Preliminary specification
SAA7390
Fig.35 Fast page mode DRAM read cycle.
Philips Semiconductors
tW;RAS
andbook, full pagewidth
1996 Jul 02
th;CAS tcy;FPR/W tW;CAS tpCAS tW;CAS tpCAS th;RAS tW;CAS
RAS
tpCAS;RAS
tdRAS;CAS
CAS
High performance Compact Disc-Recordable (CD-R) controller
thCA;RAS tdRAS;CA th;CA tsu;CA tsu;CA th;CA th;CA
tsu;RA
th;RA
tsu;CA
tCA;RASL
71
COLUMN COLUMN COLUMN th;DAT th;DAT tsu;DAT tsu;DAT th;DAT
MGE415
ADDRESS
ROW
thDAT;RAS
tsu;DAT
DATA
Preliminary specification
SAA7390
Fig.36 Fast page mode DRAM write cycle.
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
SAA7390
handbook, full pagewidth
tcy;R/W tW;RAS RAS tpCAS;RAS tpRAS;CAS tpRAS
CAS tsu;RA th;RA
ADDRESS
ROW
ROW
MGE416
Fig.37 DRAM refresh cycle.
1996 Jul 02
72
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
16 PACKAGE OUTLINE
SAA7390
SQFP128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm
SOT387-2
c y X
A 102 103 65 64
e E HE A A2 A1 (A 3) Lp pin 1 index 128 1 wM D HD B vM B 39 38 vMA bp detail X L
wM
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.40 A1 min. 0.25 A2 3.05 2.55 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.0 E (1) 14.0 e 0.50 HD 23.2 HE 17.2 L 1.60 Lp 0.95 0.65 v 0.20 w 0.08 y 0.10 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT387-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-03-14
1996 Jul 02
73
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
17 SOLDERING 17.1 Introduction 17.3 Wave soldering
SAA7390
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 17.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Repairing soldered joints
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 02
74
Philips Semiconductors
Preliminary specification
High performance Compact Disc-Recordable (CD-R) controller
18 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7390
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jul 02
75
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7390_1.copy June 26, 1996 11:51 am SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
517021/50/01/pp76 Date of release: 1996 Jul 02 Document order number: 9397 750 00942

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